Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8;
From:   Hiten Chauhan <hiten.chauhan@siliconsignals.io>
To:     jmaneyrol@invensense.com, jic23@kernel.org, lars@metafoo.de,
        linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org
Cc:     Hiten Chauhan <hiten.chauhan@siliconsignals.io>
Subject: [PATCH v2 1/1] Added tilt interrupt support in inv_icm42600
Date:   Thu, 16 Nov 2023 19:15:28 +0530
Message-Id: <20231116134528.21467-1-hiten.chauhan@siliconsignals.io>
Content-Transfer-Encoding: 7BIT
Content-Type:   text/plain; charset=US-ASCII
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?cqzlVZXwOk4VNDaEQLcMSt9zkgjXE0cBtoEnX5HUuasTss4f9IxKjMqzssrP?=
 =?us-ascii?Q?LDwIrqIfUQSkEyLIlVoCm9S47aOoKpAHIhf287kYE10Hlog7trTq+bZNJHUK?=
 =?us-ascii?Q?2xwH1rjYYKnqvRlobxjrigWzIWyIh0njvhuDRLtxst8gwj8yOhRpK57M+vdI?=
 =?us-ascii?Q?862S0y88NK4PAA0XaLfa/cxqjcya4S0XR0525SeENOxtiNH5CfbOYcVdAzDR?=
 =?us-ascii?Q?NbNBE7g8pDVTyATOtWBy2D8i3HQRZ0B60OjGj9tqAX1jzKFkzKnAEq/+O81q?=
 =?us-ascii?Q?HxUBdz1U8P3/FT/mJBQaQk3lRh1Mw5rQ6DDT4cWYIZjc+3RBxvTDReNMYwza?=
 =?us-ascii?Q?+qOhoGkv4lxZTaP8mYh818qyXg6Lx6L13m7s58JT4tZbeLQgH8wS6AdDwT+W?=
 =?us-ascii?Q?Xp08EkvJ48UoiI1434tsj4sScIXgXeVokjrym6dt5dCIelx3SaDWNBwaFQXj?=
 =?us-ascii?Q?CxuHscZTMezAzasHGjwj4cosMQkIQmHZ58qYN1t4x4WJ2it2D4GTwqt2h38R?=
 =?us-ascii?Q?ALuUvuOR72ouQYos9yPOFWFEw3amY3ubA1ZUbtX2KHF4bjqtnJbOmnvG1D1+?=
 =?us-ascii?Q?OJ1FpEZJ5mYiemzvEwtQVWB5k4n8ocQPxCCeA8LBKYs8bO6m+elmW3VjuXDA?=
 =?us-ascii?Q?bM/EMjbLLAWv7Yq8f7GkPZk+KXhZ+IAmof1TEKGtcDfgjOyE9+c+EATTp2SI?=
 =?us-ascii?Q?oo7Gn2tr6H5dmHOP2MXGQoS+shyoknEtpTsOYPa7VZJdd0At/Dj2a21wV9Qo?=
 =?us-ascii?Q?LwbtLoLdgZ1PGOR5JAdtEh42Oq8HY1wWVuC94Lclow8VfAvwqqCMRdzGylOO?=
 =?us-ascii?Q?ZC+yPM5qRG687fPqDFv2hcbJChRQVxRMm77MvJL20DJaBdFD5PfQZf3Bz/qv?=
 =?us-ascii?Q?tqwAIl/fpka2ldAwZCK4Ga0XkxCw3lU2OnWVwnSm9O4aijWCuhm5TetVHRnJ?=
 =?us-ascii?Q?LQ+86Xcv1ng0WQdT8MJ/PqBEC8F/Od6so4ZSQyRkgiX0r4LhuY81XZfFHqyJ?=
 =?us-ascii?Q?QEeBRp5fqxkHW3gKeE2v2P1JxDYEprX8qJXG1259/oGSffw/vWdYH/LfrmfJ?=
 =?us-ascii?Q?MYx5fKRpr4lWxB1fQdabR7UhUTSIvjr+if70W2tzozOE2OUSNNMvgkLa3Pck?=
 =?us-ascii?Q?QrgxOaLEzpF3PfVxmSaOWu3vaf9/fAkq0kYx332LKYPrh1nWCoNDTLmXqEWI?=
 =?us-ascii?Q?TlTMZw/M6tmcO4FRZDB8S0YgH2+T/6XghjSRAKt+muZ6SvnzicpB/Hu/19VI?=
 =?us-ascii?Q?mU3wgbYyAUXQS56p7KRShp8I7oy1UY2/+IGVveRIv4C05jnlhTEq3DlRmmHh?=
 =?us-ascii?Q?DVgMThrrxZxwEXdNvitKTqgKK7MP2JBYiV5t6YOUtldvIga0tJNYjC/8WGSk?=
 =?us-ascii?Q?M7LVm9DX7frZO9R1cUTLSEX1wPgmH3qWfbKKtLMA7Bv4x39Nr8moVrpFQKcV?=
 =?us-ascii?Q?xocIsbfmHa1/cY72IVimc45etDXhCTaq6JgyaCkY6nNjD4bBmHatfDuY3sUU?=
 =?us-ascii?Q?OCBOK/iVz0zK6lyKPsy94NlDcr4WxBwcs3ABzlsb1imrAq5JBXpIYPvKpzrz?=
 =?us-ascii?Q?YorLMruEJnzMr2Z5nDvNQ4U49NlR9DPZiszPi3nZ62G7E4Dh7p0oY04HwjH9?=
 =?us-ascii?Q?RMIAxiLMVsudGB6HIcpiKLc=3D?=
X-OriginatorOrg: siliconsignals.io
X-MS-Exchange-CrossTenant-Network-Message-Id: 1940d450-8449-4783-53cb-08dbe6aa58fd
X-MS-Exchange-CrossTenant-AuthSource: MAXPR01MB4118.INDPRD01.PROD.OUTLOOK.COM
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2023 13:45:51.6136
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 7ec5089e-a433-4bd1-a638-82ee62e21d37
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: pGr9PyhjG9V5tHCBTtve4VDkY26ydEpP03cQ1CvUxJj8MdJ58rcps31aFv5ucxiSDTPywVbwXHa/jIja1iWM2CSyZZ5wR1dy0n2dgtZUjqM=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PN3PR01MB7096
X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,
	MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE
	autolearn=unavailable autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Thu, 16 Nov 2023 05:46:28 -0800 (PST)

Description:
Add new device attribute to enable and disable
Tilt interrupt from kernel user space

Signed-off-by: Hiten Chauhan <hiten.chauhan@siliconsignals.io>

diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600.h b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
index 0e290c807b0f..39ed39e77deb 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600.h
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
@@ -187,6 +187,8 @@ struct inv_icm42600_state {
 #define INV_ICM42600_FIFO_CONFIG_STOP_ON_FULL		\
 		FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 2)
 
+#define INV_ICM42600_REG_MASK        GENMASK(7, 0)
+
 /* all sensor data are 16 bits (2 registers wide) in big-endian */
 #define INV_ICM42600_REG_TEMP_DATA			0x001D
 #define INV_ICM42600_REG_ACCEL_DATA_X			0x001F
@@ -239,6 +241,7 @@ struct inv_icm42600_state {
 #define INV_ICM42600_REG_PWR_MGMT0			0x004E
 #define INV_ICM42600_PWR_MGMT0_TEMP_DIS			BIT(5)
 #define INV_ICM42600_PWR_MGMT0_IDLE			BIT(4)
+#define INV_ICM42600_PWR_ACCEL_MODE			BIT(1)
 #define INV_ICM42600_PWR_MGMT0_GYRO(_mode)		\
 		FIELD_PREP(GENMASK(3, 2), (_mode))
 #define INV_ICM42600_PWR_MGMT0_ACCEL(_mode)		\
@@ -306,6 +309,21 @@ struct inv_icm42600_state {
 #define INV_ICM42600_WHOAMI_ICM42622			0x46
 #define INV_ICM42600_WHOAMI_ICM42631			0x5C
 
+/* Register configs for tilt interrupt */
+#define INV_ICM42605_REG_APEX_CONFIG4                  0x4043
+#define INV_ICM42605_APEX_CONFIG4_MASK                 GENMASK(7, 0)
+
+#define INV_ICM42605_REG_APEX_CONFIG0                  0x0056
+#define INV_ICM42605_APEX_CONFIG0_TILT_ENABLE          BIT(4)
+#define INV_ICM42605_APEX_CONFIG0                      BIT(1)
+
+#define INV_ICM42605_REG_INTF_CONFIG1                   0x404D
+#define INV_ICM42605_INTF_CONFIG1_MASK                  GENMASK(5, 0)
+#define INV_ICM42605_INTF_CONFIG1_TILT_DET_INT1_EN      BIT(3)
+
+#define INV_ICM42605_REG_INT_STATUS3                   0x0038
+
+
 /* User bank 1 (MSB 0x10) */
 #define INV_ICM42600_REG_SENSOR_CONFIG0			0x1003
 #define INV_ICM42600_SENSOR_CONFIG0_ZG_DISABLE		BIT(5)
@@ -364,6 +382,8 @@ typedef int (*inv_icm42600_bus_setup)(struct inv_icm42600_state *);
 extern const struct regmap_config inv_icm42600_regmap_config;
 extern const struct dev_pm_ops inv_icm42600_pm_ops;
 
+extern uint8_t inv_icm42605_int_reg;
+
 const struct iio_mount_matrix *
 inv_icm42600_get_mount_matrix(const struct iio_dev *indio_dev,
 			      const struct iio_chan_spec *chan);
@@ -395,4 +415,8 @@ struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st);
 
 int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev);
 
+int inv_icm42605_generate_tilt_interrupt(struct inv_icm42600_state *st);
+
+int inv_icm42605_disable_tilt_interrupt(struct inv_icm42600_state *st);
+
 #endif
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c
index b1e4fde27d25..7140ac967d88 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c
@@ -47,6 +47,8 @@
 		.ext_info = _ext_info,					\
 	}
 
+uint8_t inv_icm42605_int_reg;
+
 enum inv_icm42600_accel_scan {
 	INV_ICM42600_ACCEL_SCAN_X,
 	INV_ICM42600_ACCEL_SCAN_Y,
@@ -60,6 +62,69 @@ static const struct iio_chan_spec_ext_info inv_icm42600_accel_ext_infos[] = {
 	{},
 };
 
+static ssize_t tilt_interrupt_show(struct device *dev,
+			       struct device_attribute *attr, char *buf)
+{
+	struct inv_icm42600_state *st = dev_get_drvdata(dev);
+	unsigned int val;
+	int ret;
+
+	ret = regmap_read(st->map, inv_icm42605_int_reg, &val);
+
+	if (ret != 0)
+		return ret;
+
+	snprintf(buf, PAGE_SIZE, "Read reg %x value %x\n", inv_icm42605_int_reg, val);
+
+	return strlen(buf);
+}
+
+static ssize_t tilt_interrupt_store(struct device *dev,
+		struct device_attribute *attr, const char *buf,
+		size_t count)
+{
+	struct inv_icm42600_state *st = dev_get_drvdata(dev);
+	int ret;
+	int value;
+
+	if (!st)
+		return -EINVAL;
+
+	if (kstrtoint(buf, 10, &value))
+		return -EINVAL;
+
+	inv_icm42605_int_reg = INV_ICM42605_REG_INT_STATUS3;
+
+	switch (value) {
+	case 1:
+		ret = inv_icm42605_generate_tilt_interrupt(st);
+		if (ret != 0)
+			return -EIO;
+		break;
+	case 0:
+		ret = inv_icm42605_disable_tilt_interrupt(st);
+		if (ret != 0)
+			return -EIO;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return count;
+}
+
+static DEVICE_ATTR_RW(tilt_interrupt, 0644,
+		   tilt_interrupt_show, tilt_interrupt_store);
+
+static struct attribute *icm42605_attrs[] = {
+	&dev_attr_tilt_interrupt.attr,
+	NULL,
+};
+
+static const struct attribute_group icm42605_attrs_group = {
+	.attrs = icm42605_attrs,
+};
+
 static const struct iio_chan_spec inv_icm42600_accel_channels[] = {
 	INV_ICM42600_ACCEL_CHAN(IIO_MOD_X, INV_ICM42600_ACCEL_SCAN_X,
 				inv_icm42600_accel_ext_infos),
@@ -702,6 +767,7 @@ static const struct iio_info inv_icm42600_accel_info = {
 	.update_scan_mode = inv_icm42600_accel_update_scan_mode,
 	.hwfifo_set_watermark = inv_icm42600_accel_hwfifo_set_watermark,
 	.hwfifo_flush_to_buffer = inv_icm42600_accel_hwfifo_flush,
+	.attrs = &icm42605_attrs_group,
 };
 
 struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st)
@@ -791,3 +857,67 @@ int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev)
 
 	return 0;
 }
+
+int inv_icm42605_generate_tilt_interrupt(struct inv_icm42600_state *st)
+{
+	int ret;
+	int val;
+	char sleep = 10;
+
+	ret = regmap_update_bits(st->map, INV_ICM42605_REG_APEX_CONFIG4,
+				 INV_ICM42605_APEX_CONFIG4_MASK, 0);
+	if (ret)
+		return ret;
+
+	val = INV_ICM42600_PWR_ACCEL_MODE;
+	ret = regmap_write(st->map, INV_ICM42600_REG_PWR_MGMT0, val);
+	if (ret)
+		return ret;
+
+	val = INV_ICM42605_APEX_CONFIG0;
+	ret = regmap_write(st->map, INV_ICM42605_REG_APEX_CONFIG0, val);
+	if (ret)
+		return ret;
+
+	val = INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET;
+	ret = regmap_write(st->map, INV_ICM42600_REG_SIGNAL_PATH_RESET, val);
+	if (ret)
+		return ret;
+
+	msleep(sleep);
+
+	val = INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN;
+	ret = regmap_write(st->map, INV_ICM42600_REG_SIGNAL_PATH_RESET, val);
+	if (ret)
+		return ret;
+
+	val = INV_ICM42605_APEX_CONFIG0_TILT_ENABLE |
+	      INV_ICM42605_APEX_CONFIG0;
+	ret = regmap_write(st->map, INV_ICM42605_REG_APEX_CONFIG0, val);
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(st->map, INV_ICM42605_REG_INTF_CONFIG1,
+				 INV_ICM42605_INTF_CONFIG1_MASK,
+				 INV_ICM42605_INTF_CONFIG1_TILT_DET_INT1_EN);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int inv_icm42605_disable_tilt_interrupt(struct inv_icm42600_state *st)
+{
+	int ret;
+
+	ret = regmap_write(st->map, INV_ICM42605_REG_APEX_CONFIG0, 0);
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(st->map, INV_ICM42605_REG_INTF_CONFIG1,
+			INV_ICM42605_INTF_CONFIG1_MASK, 0);
+	if (ret)
+		return ret;
+
+	return 0;
+}
-- 
2.25.1