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Fri, 17 Nov 2023 04:19:57 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AH4Jvuw010760 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 04:19:57 GMT Received: from [10.79.43.91] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Thu, 16 Nov 2023 20:19:49 -0800 Message-ID: <7ab6456f-bf2d-32c1-709c-b1426c412747@quicinc.com> Date: Fri, 17 Nov 2023 09:49:46 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 5/5] arm64: defconfig: Enable SC8380XP SoC base configs Content-Language: en-US To: Krzysztof Kozlowski , , , , , , CC: , , , , , , , , , , , , , , , , , References: <20231025142427.2661-1-quic_sibis@quicinc.com> <20231025142427.2661-6-quic_sibis@quicinc.com> <75b41aca-0333-4e69-aaf2-9aaa48d18d1b@linaro.org> From: Sibi Sankar In-Reply-To: <75b41aca-0333-4e69-aaf2-9aaa48d18d1b@linaro.org> Content-Type: text/plain; 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Thu, 16 Nov 2023 20:20:29 -0800 (PST) Hey Krzysztof, On 10/27/23 13:48, Krzysztof Kozlowski wrote: > On 25/10/2023 16:24, Sibi Sankar wrote: >> From: Rajendra Nayak >> >> Enable GCC, Pinctrl and Interconnect configs for SC8380XP needed to boot >> to a console shell. > > This is generic defconfig for all platforms. You must be explicit which > SoC and board you now target. How anyone could figure out that random > set of numbers/letters like A1204XZY SoC is Qualcomm? Thanks, will fixup the commit message. -Sibi > > Best regards, > Krzysztof >