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Message-ID: <dd8260ce-3cbe-42f5-bc58-51730cd5dabd@quicinc.com>
Date:   Fri, 17 Nov 2023 17:56:24 +0800
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Subject: Re: [PATCH 1/9] net: mdio: ipq4019: increase eth_ldo_rdy for ipq5332
 platform
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        <agross@kernel.org>, <andersson@kernel.org>,
        <konrad.dybcio@linaro.org>, <davem@davemloft.net>,
        <edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <conor+dt@kernel.org>, <andrew@lunn.ch>, <hkallweit1@gmail.com>,
        <linux@armlinux.org.uk>, <robert.marko@sartura.hr>
CC:     <linux-arm-msm@vger.kernel.org>, <netdev@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <quic_srichara@quicinc.com>
References: <20231115032515.4249-1-quic_luoj@quicinc.com>
 <20231115032515.4249-2-quic_luoj@quicinc.com>
 <7786f8e0-2395-4bb6-bc29-071ed637611f@linaro.org>
From:   Jie Luo <quic_luoj@quicinc.com>
In-Reply-To: <7786f8e0-2395-4bb6-bc29-071ed637611f@linaro.org>
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On 11/16/2023 7:57 PM, Krzysztof Kozlowski wrote:
> On 15/11/2023 04:25, Luo Jie wrote:
>> There are two PCS(UNIPHY) supported in SOC side on ipq5332,
>> and three PCS(UNIPHY) supported on ipq9574.
>>
>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
>> ---
>>   drivers/net/mdio/mdio-ipq4019.c | 55 +++++++++++++++++++--------------
>>   1 file changed, 32 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c
>> index abd8b508ec16..9d444f5f7efb 100644
>> --- a/drivers/net/mdio/mdio-ipq4019.c
>> +++ b/drivers/net/mdio/mdio-ipq4019.c
>> @@ -18,28 +18,31 @@
>>   #define MDIO_DATA_WRITE_REG			0x48
>>   #define MDIO_DATA_READ_REG			0x4c
>>   #define MDIO_CMD_REG				0x50
>> -#define MDIO_CMD_ACCESS_BUSY		BIT(16)
>> -#define MDIO_CMD_ACCESS_START		BIT(8)
>> -#define MDIO_CMD_ACCESS_CODE_READ	0
>> -#define MDIO_CMD_ACCESS_CODE_WRITE	1
>> -#define MDIO_CMD_ACCESS_CODE_C45_ADDR	0
>> -#define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
>> -#define MDIO_CMD_ACCESS_CODE_C45_READ	2
>> +#define MDIO_CMD_ACCESS_BUSY			BIT(16)
>> +#define MDIO_CMD_ACCESS_START			BIT(8)
>> +#define MDIO_CMD_ACCESS_CODE_READ		0
>> +#define MDIO_CMD_ACCESS_CODE_WRITE		1
>> +#define MDIO_CMD_ACCESS_CODE_C45_ADDR		0
>> +#define MDIO_CMD_ACCESS_CODE_C45_WRITE		1
>> +#define MDIO_CMD_ACCESS_CODE_C45_READ		2
> 
> Where is anything related to ipq5332 here?

This is for alignment format, will keep it untouched in the next
patch set.

> 
> 
> ..
> 
>>   	bus->name = "ipq4019_mdio";
>>   	bus->read = ipq4019_mdio_read_c22;
>> @@ -288,6 +296,7 @@ static void ipq4019_mdio_remove(struct platform_device *pdev)
>>   static const struct of_device_id ipq4019_mdio_dt_ids[] = {
>>   	{ .compatible = "qcom,ipq4019-mdio" },
>>   	{ .compatible = "qcom,ipq5018-mdio" },
>> +	{ .compatible = "qcom,ipq5332-mdio" },
> 
> How user comes before binding?

The new added compatible is for the GCC uniphy AHB/SYS clocks configured
on the ipq5332 platform, will move this change into the following patch
that involves the ipq5332 to make it clear.

<net: mdio: ipq4019: Enable the clocks for ipq5332 platform>.

> 
> Best regards,
> Krzysztof
>