Received: by 2002:a05:7412:b130:b0:e2:908c:2ebd with SMTP id az48csp651843rdb; Fri, 17 Nov 2023 08:54:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IG8dlRgFaq6WYcRz4F/9Cmj9w39d6SoOD2Swl3YJW3Cfc5Z9blpJ0JQ/uxEoJcRUfDtSUs9 X-Received: by 2002:a17:90b:3149:b0:27d:8fbd:be8c with SMTP id ip9-20020a17090b314900b0027d8fbdbe8cmr15173pjb.28.1700240045474; Fri, 17 Nov 2023 08:54:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700240045; cv=none; d=google.com; s=arc-20160816; b=LKsGIJuDsD8CAfU/0lQV6RvIo70JfUoVO9+P/3Ez1OYsbTR5Y8J/5L4skHr6097qnW y3e3O1pe22rez8ASBP6NjHHVn+5GmJkXtQKn+KvKIBzoOwJ03oHK+HE0R8oP1oxEdi4Y efOHRaXQCTPpYc6TCpw6365ztHHqxfhZxNVvEMRAV7FdXpmuReglH3EOTSgsdUpBIWvk /hAAGndta+oxK4Ty6j+mc1/BqoDdwemxEZO2p+ONocPpDPabCu4j8JKLNU38JCdbzln7 eFsPj5qUObgMY8RHBVfBnlaxf6MzpXpEOWuf4lKEMoSuBU92zanzGc4mDMX/jy5Jx9c7 0Lgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=B4uEcE8nmP9Kr7C1JDhY6eEscZlT28hCsgsusWjKREw=; fh=pcFVTyicv/rzRPxIjZYIiiwn+nyLctuJCrnSjjaRuLI=; b=Ab+B3GEu4SmP4YSTOyw2fzlNNI1hKXS1c2OWTw0B/rG9EiiHCP/9clSE8Kw89Adl9p saeYyUBSfCJw6z7pMbBn1EKewg9BUS1HjS14rbXp8f4s6EY5u9Zln+c/LTWH4Y/3wWTJ J2kbci0Uh/4cn8OqGK3D9gm3SFMfAIMI0mAUGN0nIh8rb3oygTFIlf/rQYdZkvyhvbuK c9jidjBkdziWjczjrK/E+Agr/BtAx4lngfKA1nlf30RQyxUmaxREoBGKLjxyCuQo6t25 YcLhcgEf8jfP3eUd1d3IBUu94+bkYdDnLE/Bj8fD/Lpx+2scVgAzMCVyouDyx3qPLOgG BIqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=WRlzRdCI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id p2-20020a17090ab90200b00280824ab2e9si4645675pjr.137.2023.11.17.08.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 08:54:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=WRlzRdCI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 0D0E88089E7A; Fri, 17 Nov 2023 08:53:59 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346120AbjKQQxs (ORCPT + 99 others); Fri, 17 Nov 2023 11:53:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231580AbjKQQxr (ORCPT ); Fri, 17 Nov 2023 11:53:47 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37534D5E; Fri, 17 Nov 2023 08:53:44 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AHGrWY7075143; Fri, 17 Nov 2023 10:53:32 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1700240012; bh=B4uEcE8nmP9Kr7C1JDhY6eEscZlT28hCsgsusWjKREw=; h=From:To:CC:Subject:Date; b=WRlzRdCIO13qEQ2/PzVpDaDdB+voootjJaJffRtTVy+A/iVEtxOCLIr68yuRfH6eB KJHhhZ727YQJetPWhA8ZwF07ztsP90NdMnjLXkS/oWNtR/WFI6Xq9EocmIBjjL3a/6 HpXi4kwjnp4rJs9FRIztV+1HSiW7IwVrdbtXtFPo= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AHGrW8k050268 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Nov 2023 10:53:32 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 17 Nov 2023 10:53:32 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 17 Nov 2023 10:53:32 -0600 Received: from fllv0040.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AHGrVx9047560; Fri, 17 Nov 2023 10:53:31 -0600 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Jan Kiszka , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH] arm64: dts: ti: k3-am65: Add AM652 DTSI file Date: Fri, 17 Nov 2023 10:53:30 -0600 Message-ID: <20231117165330.98472-1-afd@ti.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Fri, 17 Nov 2023 08:53:59 -0800 (PST) The AM652 is basically a AM654 but with 2 cores instead of 4. Add a DTSI file for AM652 matching AM654 except this core difference. This removes the need to remove the extra cores from AM654 manually in DT files for boards that use the AM652 variant. Do that for the IOT2050 boards here. Signed-off-by: Andrew Davis --- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am652.dtsi | 74 +++++++++++++++++++ .../ti/k3-am6528-iot2050-basic-common.dtsi | 11 +-- .../ti/k3-am6548-iot2050-advanced-common.dtsi | 1 + 4 files changed, 76 insertions(+), 11 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am652.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index ba1c14a54acf4..bd5273a37b095 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -9,7 +9,6 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2 */ -#include "k3-am654.dtsi" #include / { diff --git a/arch/arm64/boot/dts/ti/k3-am652.dtsi b/arch/arm64/boot/dts/ti/k3-am652.dtsi new file mode 100644 index 0000000000000..0f22e00faa903 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am652.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM65 SoC family in Dual core configuration + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am65.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + + thermal_zones: thermal-zones { + #include "k3-am654-industrial-thermal.dtsi" + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi index 5ab434c02ab6b..feb0eae4e6df4 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi @@ -9,6 +9,7 @@ * Common bits of the IOT2050 Basic variant, PG1 and PG2 */ +#include "k3-am652.dtsi" #include "k3-am65-iot2050-common.dtsi" / { @@ -17,16 +18,6 @@ memory@80000000 { /* 1G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x40000000>; }; - - cpus { - cpu-map { - /delete-node/ cluster1; - }; - /delete-node/ cpu@100; - /delete-node/ cpu@101; - }; - - /delete-node/ l2-cache1; }; /* eMMC */ diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi index be55494b1f3fc..ff2fdc2e12e3c 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -11,6 +11,7 @@ /dts-v1/; +#include "k3-am654.dtsi" #include "k3-am65-iot2050-common.dtsi" / { -- 2.39.2