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([2a01:e0a:982:cbb0:203f:8c0f:b03c:8d45]) by smtp.gmail.com with ESMTPSA id f11-20020a05600c4e8b00b0040535648639sm10774533wmq.36.2023.11.19.09.59.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 19 Nov 2023 09:59:37 -0800 (PST) Message-ID: <26df42ac-edb0-ac72-d5cb-4a4ae6819736@linaro.org> Date: Sun, 19 Nov 2023 18:59:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0 To: Konrad Dybcio , Dmitry Baryshkov , Tengfei Fan , agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, tglx@linutronix.de Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, -cc=kernel@quicinc.com References: <20231117101817.4401-1-quic_tengfan@quicinc.com> <20231117101817.4401-8-quic_tengfan@quicinc.com> <37a3a407-07e7-49d8-bbce-b1dac8cfcf5a@linaro.org> <247f4654-ec65-4857-8b35-1a79088e8b87@linaro.org> <1ae2da80-77e8-487a-a94d-b329e6f48360@linaro.org> Content-Language: en-GB From: Neil Armstrong In-Reply-To: <1ae2da80-77e8-487a-a94d-b329e6f48360@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Sun, 19 Nov 2023 09:59:53 -0800 (PST) Le 18/11/2023 à 01:08, Konrad Dybcio a écrit : > On 17.11.2023 11:41, neil.armstrong@linaro.org wrote: >> On 17/11/2023 11:29, Dmitry Baryshkov wrote: >>> On 17/11/2023 12:18, Tengfei Fan wrote: >>>> Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected, >>>> thus skip pcie_1_phy_aux_clk input clock to GCC. >>>> >>>> Signed-off-by: Tengfei Fan >>>> --- >>>>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 32 ++++++++++++++++++++++ >>>>   1 file changed, 32 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts >>>> index 202b979da8ca..3aca0a433a00 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts >>>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts >>>> @@ -393,6 +393,38 @@ >>>>       }; >>>>   }; >>>> +&gcc { >>>> +    clocks = <&bi_tcxo_div2>, <&sleep_clk>, >>>> +         <&pcie0_phy>, >>>> +         <&pcie1_phy>, >>>> +         <0>, >>>> +         <&ufs_mem_phy 0>, >>>> +         <&ufs_mem_phy 1>, >>>> +         <&ufs_mem_phy 2>, >>>> +         <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; >>>> +}; >>> >>> NAK, this should go to sm8550.dtsi unless there is a good reason. >> >> Actually this is how QRD8550 was designed, so it's fine to mimic. > Does CCF not handle this gracefully? CCF handles this very gracefully and it's a perfectly valid DT in regard to the bindings... neil > > Konrad