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Mon, 20 Nov 2023 06:42:57 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AK6gue9008974 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 20 Nov 2023 06:42:56 GMT Received: from [10.79.43.91] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 19 Nov 2023 22:42:51 -0800 Message-ID: <4af8e7a4-0506-a08c-f294-d055fb463af8@quicinc.com> Date: Mon, 20 Nov 2023 12:12:48 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH V2 2/4] clk: qcom: Add Global Clock controller (GCC) driver for X1E80100 Content-Language: en-US To: Bryan O'Donoghue , Konrad Dybcio , , , , , , Dmitry Baryshkov CC: , , , , , , , , , , References: <20231117092737.28362-1-quic_sibis@quicinc.com> <20231117092737.28362-3-quic_sibis@quicinc.com> <2e0d2c55-fb2f-4903-a555-f51019942c6e@linaro.org> From: Sibi Sankar In-Reply-To: Content-Type: text/plain; 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Sun, 19 Nov 2023 22:43:12 -0800 (PST) On 11/18/23 07:22, Bryan O'Donoghue wrote: > On 18/11/2023 00:06, Konrad Dybcio wrote: >> On 17.11.2023 21:50, Bryan O'Donoghue wrote: >>> On 17/11/2023 09:27, Sibi Sankar wrote: >>>> * Use shared ops in the x1e80100 gcc driver [Bryan]. >>> >>> This looks better to me now / more consistent with what we have in >>> sc8280xp - where we do try to hit suspend and => retention/parking >>> matters. >> Parking the clock is separate from putting the system to sleep. > > Yes but several of our clocks want to be parked, not switched off.. > which obviously does matter in suspend. > >> IIUC we usually use shared ops on clocks that may have different users >> (e.g. not only controlled by Linux) and/or that are crucial to the >> functioning of hardware (like AXI clocks, which if gated would make >> the system crash on any access attempt, from any subsystem, unless >> turned on beforehand) > > My question here for Sibi, is why sdcc2_apss_clk_src differs here from > sc8280xp? > > Is it wrong on sc8280xp or if correct sc8280xp then why is it not > replicated here ? > > https://lore.kernel.org/linux-arm-msm/e857c853-51ef-8314-2a21-fa6fd25162ca@quicinc.com/ Bryan, 5e4b7e82d497 ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") The floor_ops was introduced in sdm845 ^^ and later propagated to all other QC SoCs later on. It makes sense to do the same for sc8280xp as well. > > Also @Sibi I realise alot of this code is autogenerated - it would be > worthwhile finding/fixing the script that does the generation to plug in > shared_ops instead of floor_ops if the input material has the necessary > flags. floor_ops part isn't auto-generated (it comes out as shared_ops, but like you said it might make sense to include it as part of the generation process itself. -Sibi > > --- > bod