Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5;
Message-ID: <2d4818f6-3935-4621-bf96-d84747cbefa3@quicinc.com>
Date:   Mon, 20 Nov 2023 17:00:13 +0800
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH 9/9] dt-bindings: net: ipq4019-mdio: Document ipq5332
 platform
Content-Language: en-US
To:     Andrew Lunn <andrew@lunn.ch>
CC:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        <agross@kernel.org>, <andersson@kernel.org>,
        <konrad.dybcio@linaro.org>, <davem@davemloft.net>,
        <edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <conor+dt@kernel.org>, <hkallweit1@gmail.com>,
        <linux@armlinux.org.uk>, <robert.marko@sartura.hr>,
        <linux-arm-msm@vger.kernel.org>, <netdev@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <quic_srichara@quicinc.com>
References: <20231115032515.4249-1-quic_luoj@quicinc.com>
 <20231115032515.4249-10-quic_luoj@quicinc.com>
 <834cbb58-3a88-4ba6-8db6-10440a4d0893@linaro.org>
 <76e081ba-9d5a-41df-9c1b-d782e5656973@quicinc.com>
 <2a9bb683-da73-47af-8800-f14a833e8ee4@linaro.org>
 <386fcee0-1eab-4c0b-8866-a67821a487ee@quicinc.com>
 <77a194cd-d6a4-4c9b-87f5-373ed335528f@linaro.org>
 <de4fa95e-4bc7-438a-94bb-4b31b1b89704@quicinc.com>
 <6e10604f-d463-499b-b00a-57ef22a936bb@lunn.ch>
From:   Jie Luo <quic_luoj@quicinc.com>
In-Reply-To: <6e10604f-d463-499b-b00a-57ef22a936bb@lunn.ch>
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 7bit
Precedence: bulk


On 11/18/2023 11:36 PM, Andrew Lunn wrote:
>> The clock arguments are provided in the later part as below. i will also
>> provide more detail clock names for the new added clocks for the ipq5332
>> platform in description.
>>
>>    - if:
>>
>>        properties:
>>
>>          compatible:
>>
>>            contains:
>>
>>              enum:
>>
>>                - qcom,ipq5332-mdio
>>
>>      then:
>>
>>        properties:
>>
>>          clocks:
>>
>>            items:
>>
>>              - description: MDIO clock source frequency fixed to 100MHZ
>>
>>              - description: UNIPHY0 AHB clock source frequency fixed to
>> 100MHZ
>>              - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ
>>              - description: UNIPHY1 AHB clock source frequency fixed to
>> 100MHZ
>>              - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ
> 
> As i said before, the frequency of the clocks does not matter
> here. That appears to be the drivers problem. I assume every board
> design, with any sort of PHY, needs the same clock configuration?
> 
>        Andrew

Yes, Andrew, no matter what kind of PHY is connected, these clocks are
fix clocks, the clock rates are same as mentioned above, which are the 
SOC clock configurations.