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Mon, 20 Nov 2023 10:06:52 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AKA6plj004941 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 20 Nov 2023 10:06:51 GMT Received: from [10.218.10.86] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 20 Nov 2023 02:06:43 -0800 Message-ID: <5eae728f-f052-f2aa-7876-cb2421191fc9@quicinc.com> Date: Mon, 20 Nov 2023 15:36:40 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v8 0/5] arm64: qcom: sa8775p: add support for EP PCIe To: , , , , , , CC: , , , , , , , , , , , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Kishon Vijay Abraham I , , , , , References: <1699669982-7691-1-git-send-email-quic_msarkar@quicinc.com> Content-Language: en-US From: Mrinmay Sarkar In-Reply-To: <1699669982-7691-1-git-send-email-quic_msarkar@quicinc.com> Content-Type: text/plain; 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Mon, 20 Nov 2023 02:07:33 -0800 (PST) Some of the patches are reviewed. Please apply in linux-next. Thanks, Mrinmay On 11/11/2023 8:02 AM, Mrinmay Sarkar wrote: > This series adds the relavent DT bindings, new compatible string, > add support to EPF driver and add EP PCIe node in dtsi file for > ep pcie0 controller. > > v7 -> v8: > - Add new patch PCI: epf-mhi: Add "pci_epf_mhi_" prefix to the function > names > - Update PCI: epf-mhi: Add support for SA8775P patch on top of the new > patch and update commit message. > > v6 -> v7: > - add reviewed by tag in commit message in all patches. > - update commit message in patch 2 as per comment. > - update reason for reusing PID in commit message. > > v5 -> v6: > - update cover letter. > > v4 -> v5: > - add maxItems to the respective field to constrain io space and > interrupt in all variants. > > v3 -> v4: > - add maxItems field in dt bindings > - update comment in patch2 > - dropped PHY driver patch as it is already applied [1] > - update comment in EPF driver patch > - update commect in dtsi and add iommus instead of iommu-map > > [1] https://lore.kernel.org/all/169804254205.383714.18423881810869732517.b4-ty@kernel.org/ > > v2 -> v3: > - removed if/then schemas, added minItems for reg, > reg-bnames, interrupt and interrupt-names instead. > - adding qcom,sa8775p-pcie-ep compitable for sa8775p > as we have some specific change to add. > - reusing sm8450's pcs_misc num table as it is same as sa8775p. > used appropriate namespace for pcs. > - remove const from sa8775p_header as kernel test robot > throwing some warnings due to this. > - remove fallback compatiable as we are adding compatiable for sa8775p. > > v1 -> v2: > - update description for dma > - Reusing qcom,sdx55-pcie-ep compatibe so remove compaitable > for sa8775p > - sort the defines in phy header file and remove extra defines > - add const in return type pci_epf_header and remove MHI_EPF_USE_DMA > flag as hdma patch is not ready > - add fallback compatiable as qcom,sdx55-pcie-ep, add iommu property > > > Mrinmay Sarkar (5): > dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC > PCI: qcom-ep: Add support for SA8775P SOC > PCI: epf-mhi: Add "pci_epf_mhi_" prefix to the function names > PCI: epf-mhi: Add support for SA8775P > arm64: dts: qcom: sa8775p: Add ep pcie0 controller node > > .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 64 +++++++++++++++++++++- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 ++++++++++++++++ > drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + > drivers/pci/endpoint/functions/pci-epf-mhi.c | 21 ++++++- > 4 files changed, 128 insertions(+), 4 deletions(-) >