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Tue, 21 Nov 2023 00:51:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AL0pVRf008762 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 00:51:31 GMT Received: from [10.239.132.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 20 Nov 2023 16:51:28 -0800 Message-ID: <732c55bb-e4a5-4a09-9b7b-0e615ddd580c@quicinc.com> Date: Tue, 21 Nov 2023 08:51:26 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0 To: Krzysztof Kozlowski , , , , , , , CC: , , , <-cc=kernel@quicinc.com> References: <20231117101817.4401-1-quic_tengfan@quicinc.com> <20231117101817.4401-8-quic_tengfan@quicinc.com> <61977f5a-fc04-4f85-8b18-a11df3a6b5ec@linaro.org> From: Tengfei Fan In-Reply-To: <61977f5a-fc04-4f85-8b18-a11df3a6b5ec@linaro.org> Content-Type: text/plain; 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Mon, 20 Nov 2023 16:51:48 -0800 (PST) 在 11/17/2023 6:30 PM, Krzysztof Kozlowski 写道: > On 17/11/2023 11:18, Tengfei Fan wrote: >> Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, >> thus skip pcie_1_phy_aux_clk input clock to GCC. >> >> Signed-off-by: Tengfei Fan > > You just added this board. Does it mean you added incomplete and wrong DTSU? > > Best regards, > Krzysztof > Hi Krzysztof, I will drop PCIe1 setting in dts file because of PCIe1 still have not enable in dts file. Another I understand what your comments means is I should combine all the functions which should be implemented together and submit as a complete patch, right? I will combine all the functions patch to a total patch when I do next version patch series, because there is another your comments also want to me do as so. -- Thx and BRs, Tengfei Fan