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Tue, 21 Nov 2023 01:03:45 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AL13imJ003959 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 01:03:44 GMT Received: from [10.239.132.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 20 Nov 2023 17:03:42 -0800 Message-ID: <40b86f99-3d55-4237-8638-de7efacfc307@quicinc.com> Date: Tue, 21 Nov 2023 09:03:39 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 12/16] arm64: dts: qcom: sm8550-aim300: enable PMIC Volume and Power buttons To: Krzysztof Kozlowski , , , , , , , CC: , , , <-cc=kernel@quicinc.com> References: <20231117101817.4401-1-quic_tengfan@quicinc.com> <20231117101817.4401-13-quic_tengfan@quicinc.com> From: Tengfei Fan In-Reply-To: Content-Type: text/plain; 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Mon, 20 Nov 2023 17:04:01 -0800 (PST) 在 11/17/2023 6:32 PM, Krzysztof Kozlowski 写道: > On 17/11/2023 11:18, Tengfei Fan wrote: >> The Volume Down & Power buttons are controlled by the PMIC via the PON >> hardware, and the Volume Up is connected to a PMIC gpio. >> >> Enable the necessary hardware and setup the GPIO state for the Volume Up >> gpio key. >> >> Signed-off-by: Tengfei Fan >> --- > > No, really, necessary hardware? So why it is missing in the previous patch? > > Stop useless splitting of work which is done. You cannot have "release > late, release often". The rule is: "release early, release often". > > NAK. > > Best regards, > Krzysztof > Hi Krzysztof, In next version patch series, I'm going to combine all the splited functions into one patch. -- Thx and BRs, Tengfei Fan