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Date:   Tue, 21 Nov 2023 10:49:17 +0100
From:   =?UTF-8?B?S8O2cnk=?= Maincent <kory.maincent@bootlin.com>
To:     Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Cc:     Jisheng Zhang <jszhang@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Lu jicong <jiconglu58@gmail.com>,
        "linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH] usb: dwc3: don't reset device side if dwc3 was
 configured as host-only
Message-ID: <20231121104917.0fd67952@kmaincent-XPS-13-7390>
In-Reply-To: <20231117015527.jqoh6i3n4ywg7qui@synopsys.com>
References: <20231116174206.1a823aa3@kmaincent-XPS-13-7390>
        <20231116175959.71f5d060@kmaincent-XPS-13-7390>
        <20231117014038.kbcfnpiefferqomk@synopsys.com>
        <20231117015527.jqoh6i3n4ywg7qui@synopsys.com>
Organization: bootlin
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Precedence: bulk

Hello Thinh,

On Fri, 17 Nov 2023 01:55:30 +0000
Thinh Nguyen <Thinh.Nguyen@synopsys.com> wrote:

> > How many ports do you use? Can you try this:
> >=20
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index 0328c86ef806..9921c2737829 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -296,23 +296,28 @@ int dwc3_core_soft_reset(struct dwc3 *dwc)
> >  	if (dwc->dr_mode =3D=3D USB_DR_MODE_HOST) {
> >  		u32 usb3_port;
> >  		u32 usb2_port;
> > +		int i;
> > =20
> > -		usb3_port =3D dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
> > -		usb3_port |=3D DWC3_GUSB3PIPECTL_PHYSOFTRST;
> > -		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
> > +		for (i =3D 0; i < 16; i++) {
> > +			usb3_port =3D dwc3_readl(dwc->regs,
> > DWC3_GUSB3PIPECTL(i));
> > +			usb3_port |=3D DWC3_GUSB3PIPECTL_PHYSOFTRST;
> > +			dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i),
> > usb3_port);=20
> > -		usb2_port =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> > -		usb2_port |=3D DWC3_GUSB2PHYCFG_PHYSOFTRST;
> > -		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
> > +			usb2_port =3D dwc3_readl(dwc->regs,
> > DWC3_GUSB2PHYCFG(i));
> > +			usb2_port |=3D DWC3_GUSB2PHYCFG_PHYSOFTRST;
> > +			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i),
> > usb2_port);
> > +		}
> > =20
> >  		/* Small delay for phy reset assertion */
> >  		usleep_range(1000, 2000);
> > =20
> > -		usb3_port &=3D ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
> > -		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
> > +		for (i =3D 0; i < 16; i++) {
> > +			usb3_port &=3D ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
> > +			dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i),
> > usb3_port);=20
> > -		usb2_port &=3D ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
> > -		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
> > +			usb2_port &=3D ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
> > +			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i),
> > usb2_port);
> > +		}
> > =20
> >  		/* Wait for clock synchronization */
> >  		msleep(50);
> > -- =20

Still not working on my side.

Regards,
--=20
K=C3=B6ry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com