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Subject: Re: [PATCH 12/12] RISC-V: crypto: add Zvkb accelerated ChaCha20
 implementation
From:   Jerry Shih <jerry.shih@sifive.com>
In-Reply-To: <20231120191856.GA964@sol.localdomain>
Date:   Tue, 21 Nov 2023 18:55:07 +0800
Cc:     Paul Walmsley <paul.walmsley@sifive.com>, palmer@dabbelt.com,
        Albert Ou <aou@eecs.berkeley.edu>, herbert@gondor.apana.org.au,
        davem@davemloft.net, andy.chiu@sifive.com, greentime.hu@sifive.com,
        conor.dooley@microchip.com, guoren@kernel.org, bjorn@rivosinc.com,
        heiko@sntech.de, ardb@kernel.org, phoebe.chen@sifive.com,
        hongrong.hsu@sifive.com, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org
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References: <20231025183644.8735-1-jerry.shih@sifive.com>
 <20231025183644.8735-13-jerry.shih@sifive.com>
 <20231102054327.GH1498@sol.localdomain>
 <90E2B1B4-ACC1-4316-81CD-E919D3BD03BA@sifive.com>
 <20231120191856.GA964@sol.localdomain>
To:     Eric Biggers <ebiggers@kernel.org>
Precedence: bulk

On Nov 21, 2023, at 03:18, Eric Biggers <ebiggers@kernel.org> wrote:
> First, I can see your updated patchset at branch
> "dev/jerrys/vector-crypto-upstream-v2" of =
https://github.com/JerryShih/linux,
> but I haven't seen it on the mailing list yet.  Are you planning to =
send it out?

I will send it out soon.

> Second, with your updated patchset, I'm not seeing any of the RISC-V =
optimized
> algorithms be registered when I boot the kernel in QEMU.  This is =
caused by the
> new check 'riscv_isa_extension_available(NULL, ZICCLSM)' not passing.  =
Is
> checking for "Zicclsm" the correct way to determine whether unaligned =
memory
> accesses are supported?
>=20
> I'm using 'qemu-system-riscv64 -cpu max -machine virt', with the very =
latest
> QEMU commit (af9264da80073435), so it should have all the CPU =
features.
>=20
> - Eric

Sorry, I just use my `internal` qemu with vector-crypto and rva22 =
patches.

The public qemu haven't supported rva22 profiles. Here is the qemu =
patch[1] for
that. But here is the discussion why the qemu doesn't export these
`named extensions`(e.g. Zicclsm).
I try to add Zicclsm in DT in the v2 patch set. Maybe we will have more =
discussion
about the rva22 profiles in kernel DT.

[1]
LINK: =
https://lore.kernel.org/all/d1d6f2dc-55b2-4dce-a48a-4afbbf6df526@ventanami=
cro.com/#t

I don't know whether it's a good practice to check unaligned access =
using
`Zicclsm`.=20

Here is another related cpu feature for unaligned access:
RISCV_HWPROBE_MISALIGNED_*
But it looks like it always be initialized with =
`RISCV_HWPROBE_MISALIGNED_SLOW`[2].
It implies that linux kernel always supports unaligned access. But we =
have the
actual HW which doesn't support unaligned access for vector unit.

[2]
LINK: =
https://github.com/torvalds/linux/blob/98b1cc82c4affc16f5598d4fa14b1858671=
b2263/arch/riscv/kernel/cpufeature.c#L575

I will still use `Zicclsm` checking in this stage for reviewing. And I =
will create qemu
branch with Zicclsm enabled feature for testing.

-Jerry=