Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8;
Date:   Tue, 21 Nov 2023 13:14:47 +0000
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Jerry Shih <jerry.shih@sifive.com>
CC:     Eric Biggers <ebiggers@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        <herbert@gondor.apana.org.au>, <davem@davemloft.net>,
        <andy.chiu@sifive.com>, <greentime.hu@sifive.com>,
        <guoren@kernel.org>, <bjorn@rivosinc.com>, <heiko@sntech.de>,
        <ardb@kernel.org>, <phoebe.chen@sifive.com>,
        <hongrong.hsu@sifive.com>, <linux-riscv@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <linux-crypto@vger.kernel.org>
Subject: Re: [PATCH 12/12] RISC-V: crypto: add Zvkb accelerated ChaCha20
 implementation
Message-ID: <20231121-knelt-resource-5d71c9246015@wendy>
References: <20231025183644.8735-1-jerry.shih@sifive.com>
 <20231025183644.8735-13-jerry.shih@sifive.com>
 <20231102054327.GH1498@sol.localdomain>
 <90E2B1B4-ACC1-4316-81CD-E919D3BD03BA@sifive.com>
 <20231120191856.GA964@sol.localdomain>
 <9724E3A5-F43C-4239-9031-2B33B72C4EF4@sifive.com>
MIME-Version: 1.0
Content-Type: multipart/signed; micalg=pgp-sha256;
        protocol="application/pgp-signature"; boundary="FNeg8t0GItiNFb8F"
Content-Disposition: inline
In-Reply-To: <9724E3A5-F43C-4239-9031-2B33B72C4EF4@sifive.com>
Precedence: bulk

--FNeg8t0GItiNFb8F
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable

On Tue, Nov 21, 2023 at 06:55:07PM +0800, Jerry Shih wrote:
> On Nov 21, 2023, at 03:18, Eric Biggers <ebiggers@kernel.org> wrote:
> > First, I can see your updated patchset at branch
> > "dev/jerrys/vector-crypto-upstream-v2" of https://github.com/JerryShih/=
linux,
> > but I haven't seen it on the mailing list yet.  Are you planning to sen=
d it out?
>=20
> I will send it out soon.
>=20
> > Second, with your updated patchset, I'm not seeing any of the RISC-V op=
timized
> > algorithms be registered when I boot the kernel in QEMU.  This is cause=
d by the
> > new check 'riscv_isa_extension_available(NULL, ZICCLSM)' not passing.  =
Is
> > checking for "Zicclsm" the correct way to determine whether unaligned m=
emory
> > accesses are supported?
> >=20
> > I'm using 'qemu-system-riscv64 -cpu max -machine virt', with the very l=
atest
> > QEMU commit (af9264da80073435), so it should have all the CPU features.
> >=20
> > - Eric
>=20
> Sorry, I just use my `internal` qemu with vector-crypto and rva22 patches.
>=20
> The public qemu haven't supported rva22 profiles. Here is the qemu patch[=
1] for
> that. But here is the discussion why the qemu doesn't export these
> `named extensions`(e.g. Zicclsm).
> I try to add Zicclsm in DT in the v2 patch set. Maybe we will have more d=
iscussion
> about the rva22 profiles in kernel DT.

Please do, that'll be fun! Please take some time to read what the
profiles spec actually defines Zicclsm fore before you send those patches
though. I think you might come to find you have misunderstood what it
means - certainly I did the first time I saw it!

> [1]
> LINK: https://lore.kernel.org/all/d1d6f2dc-55b2-4dce-a48a-4afbbf6df526@ve=
ntanamicro.com/#t
>=20
> I don't know whether it's a good practice to check unaligned access using
> `Zicclsm`.=20
>=20
> Here is another related cpu feature for unaligned access:
> RISCV_HWPROBE_MISALIGNED_*
> But it looks like it always be initialized with `RISCV_HWPROBE_MISALIGNED=
_SLOW`[2].
> It implies that linux kernel always supports unaligned access. But we hav=
e the
> actual HW which doesn't support unaligned access for vector unit.

https://docs.kernel.org/arch/riscv/uabi.html#misaligned-accesses

Misaligned accesses are part of the user ABI & the hwprobe stuff for
that allows userspace to figure out whether they're fast (likely
implemented in hardware), slow (likely emulated in firmware) or emulated
in the kernel.

Cheers,
Conor.

>=20
> [2]
> LINK: https://github.com/torvalds/linux/blob/98b1cc82c4affc16f5598d4fa14b=
1858671b2263/arch/riscv/kernel/cpufeature.c#L575
>=20
> I will still use `Zicclsm` checking in this stage for reviewing. And I wi=
ll create qemu
> branch with Zicclsm enabled feature for testing.
>=20
> -Jerry

--FNeg8t0GItiNFb8F
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZVytRwAKCRB4tDGHoIJi
0viAAQCm6torPYuop5E8J3sRPB3YDXMGHN9Gh2sazUdwj0zlUwEAxM05T+vdP99R
n2EWjF1PVPMc7VvyvoGGBnXDNYZ8GQE=
=cEix
-----END PGP SIGNATURE-----

--FNeg8t0GItiNFb8F--