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Tue, 21 Nov 2023 18:40:35 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ALIeYnZ003920 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 18:40:34 GMT Received: from abhinavk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 21 Nov 2023 10:40:34 -0800 From: Abhinav Kumar To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" , Bjorn Andersson , "Kuogee Hsieh" , Bjorn Andersson CC: Abhinav Kumar , Johan Hovold , , , , , , Doug Anderson , Rob Clark Subject: Re: [PATCH] drm/msm/dpu: Add missing safe_lut_tbl in sc8280xp catalog Date: Tue, 21 Nov 2023 10:40:23 -0800 Message-ID: <170059186277.16750.2750065361264739153.b4-ty@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231030-sc8280xp-dpu-safe-lut-v1-1-6d485d7b428f@quicinc.com> References: <20231030-sc8280xp-dpu-safe-lut-v1-1-6d485d7b428f@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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Tue, 21 Nov 2023 10:41:14 -0800 (PST) On Mon, 30 Oct 2023 16:23:20 -0700, Bjorn Andersson wrote: > During USB transfers on the SC8280XP __arm_smmu_tlb_sync() is seen to > typically take 1-2ms to complete. As expected this results in poor > performance, something that has been mitigated by proposing running the > iommu in non-strict mode (boot with iommu.strict=0). > > This turns out to be related to the SAFE logic, and programming the QOS > SAFE values in the DPU (per suggestion from Rob and Doug) reduces the > TLB sync time to below 10us, which means significant less time spent > with interrupts disabled and a significant boost in throughput. > > [...] Applied, thanks! [1/1] drm/msm/dpu: Add missing safe_lut_tbl in sc8280xp catalog https://gitlab.freedesktop.org/drm/msm/-/commit/a33b2431d11b Best regards, -- Abhinav Kumar