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Wed, 22 Nov 2023 08:07:14 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AM87E9R000728 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 08:07:14 GMT Received: from [10.216.60.121] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 22 Nov 2023 00:07:10 -0800 Message-ID: Date: Wed, 22 Nov 2023 13:37:07 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/8] arm64: dts: qcom: add initial SM8650 dtsi To: Neil Armstrong , Konrad Dybcio CC: , , Andy Gross , Conor Dooley , Krzysztof Kozlowski , Rob Herring , , Bjorn Andersson References: <20231121-topic-sm8650-upstream-dt-v3-0-db9d0507ffd3@linaro.org> <20231121-topic-sm8650-upstream-dt-v3-2-db9d0507ffd3@linaro.org> Content-Language: en-US From: Krishna Kurapati PSSNV In-Reply-To: <20231121-topic-sm8650-upstream-dt-v3-2-db9d0507ffd3@linaro.org> Content-Type: text/plain; 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Wed, 22 Nov 2023 00:08:28 -0800 (PST) > + > + usb_1: usb@a6f8800 { > + compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + > + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 15 IRQ_TYPE_EDGE_RISING>, > + <&pdc 14 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "hs_phy_irq", Hi Neil, This GIC_SPI 130 is actually pwr_event IRQ, not hs_phy_irq. > + "ss_phy_irq", > + "dm_hs_phy_irq", > + "dp_hs_phy_irq"; > + Regards, Krishna,