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[2620:137:e000::3:2]) by mx.google.com with ESMTPS id y15-20020a056870a34f00b001dd20d1c024si4518292oak.325.2023.11.22.05.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 05:04:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 44AF881B6D66; Wed, 22 Nov 2023 05:04:24 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344200AbjKVNEJ (ORCPT + 99 others); Wed, 22 Nov 2023 08:04:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343868AbjKVNEI (ORCPT ); Wed, 22 Nov 2023 08:04:08 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F291810C; Wed, 22 Nov 2023 05:04:01 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6C11B1595; Wed, 22 Nov 2023 05:04:48 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.43.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 45A273F7A6; Wed, 22 Nov 2023 05:04:00 -0800 (PST) Date: Wed, 22 Nov 2023 13:03:57 +0000 From: Mark Rutland To: Ian Rogers Cc: Marc Zyngier , Hector Martin , Arnaldo Carvalho de Melo , James Clark , linux-perf-users@vger.kernel.org, LKML , Asahi Linux Subject: Re: [REGRESSION] Perf (userspace) broken on big.LITTLE systems since v6.5 Message-ID: References: <08f1f185-e259-4014-9ca4-6411d5c1bc65@marcan.st> <86pm03z0kw.wl-maz@kernel.org> <86o7fnyvrq.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 22 Nov 2023 05:04:24 -0800 (PST) On Tue, Nov 21, 2023 at 08:38:45AM -0800, Ian Rogers wrote: > On Tue, Nov 21, 2023 at 8:15 AM Mark Rutland wrote: > > > > On Tue, Nov 21, 2023 at 08:09:37AM -0800, Ian Rogers wrote: > > > On Tue, Nov 21, 2023 at 8:03 AM Mark Rutland wrote: > > > > > > > > On Tue, Nov 21, 2023 at 07:46:57AM -0800, Ian Rogers wrote: > > > > > On Tue, Nov 21, 2023 at 7:40 AM Mark Rutland wrote: > > > > > > > > > > > > On Tue, Nov 21, 2023 at 03:24:25PM +0000, Marc Zyngier wrote: > > > > > > > On Tue, 21 Nov 2023 13:40:31 +0000, > > > > > > > Marc Zyngier wrote: > > > > > > > > > > > > > > > > [Adding key people on Cc] > > > > > > > > > > > > > > > > On Tue, 21 Nov 2023 12:08:48 +0000, > > > > > > > > Hector Martin wrote: > > > > > > > > > > > > > > > > > > Perf broke on all Apple ARM64 systems (tested almost everything), and > > > > > > > > > according to maz also on Juno (so, probably all big.LITTLE) since v6.5. > > > > > > > > > > > > > > > > I can confirm that at least on 6.7-rc2, perf is pretty busted on any > > > > > > > > asymmetric ARM platform. It isn't clear what criteria is used to pick > > > > > > > > the PMU, but nothing works anymore. > > > > > > > > > > > > > > > > The saving grace in my case is that Debian still ships a 6.1 perftool > > > > > > > > package, but that's obviously not going to last. > > > > > > > > > > > > > > > > I'm happy to test potential fixes. > > > > > > > > > > > > > > At Mark's request, I've dumped a couple of perf (as of -rc2) runs with > > > > > > > -vvv. And it is quite entertaining (this is taskset to an 'icestorm' > > > > > > > CPU): > > > > > > > > > > > > IIUC the tool is doing the wrong thing here and overriding explicit > > > > > > ${pmu}/${event}/ events with PERF_TYPE_HARDWARE events rather than events using > > > > > > that ${pmu}'s type and event namespace. > > > > > > > > > > > > Regardless of the *new* ABI that allows PERF_TYPE_HARDWARE events to be > > > > > > targetted to a specific PMU, it's semantically wrong to rewrite events like > > > > > > this since ${pmu}/${event}/ is not necessarily equivalent to a similarly-named > > > > > > PERF_COUNT_HW_${EVENT}. > > > > > > > > > > If you name a PMU and an event then the event should only be opened on > > > > > that PMU, 100% agree. There's a bunch of output, but when the legacy > > > > > cycles event is opened it appears to be because it was explicitly > > > > > requested. > > > > > > > > I think you've missed that the named PMU events are being erreously transformed > > > > into PERF_TYPE_HARDWARE events. Look at the -vvv output, e.g. > > > > > > > > Opening: apple_firestorm_pmu/cycles/ > > > > ------------------------------------------------------------ > > > > perf_event_attr: > > > > type 0 (PERF_TYPE_HARDWARE) > > > > size 136 > > > > config 0 (PERF_COUNT_HW_CPU_CYCLES) > > > > sample_type IDENTIFIER > > > > read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING > > > > disabled 1 > > > > inherit 1 > > > > enable_on_exec 1 > > > > exclude_guest 1 > > > > ------------------------------------------------------------ > > > > sys_perf_event_open: pid 1045843 cpu -1 group_fd -1 flags 0x8 = 4 > > > > > > > > ... which should not be PERF_TYPE_HARDWARE && PERF_COUNT_HW_CPU_CYCLES. > > > > > > > > Marc said that he bisected the issue down to commit: > > > > > > > > 5ea8f2ccffb23983 ("perf parse-events: Support hardware events as terms") > > > > > > > > ... so it looks like something is going wrong when the events are being parsed, > > > > e.g. losing the HW PMU information? > > > > > > Ok, I think I'm getting confused by other things. This looks like the issue. > > > > > > I think it may be working as intended, but not how you intended :-) If > > > a core PMU is listed and then a legacy event, the legacy event should > > > be opened on the core PMU as a legacy event with the extended type > > > set. This is to allow things like legacy cache events to be opened on > > > a specified PMU. Legacy event names match with a higher priority than > > > those in sysfs or json as they are hard coded. > > > > That has never been the case previously, so this is user-visible breakage, and > > it prevents users from being able to do the right thing, so I think that's a > > broken design. > > So the problem was caused by ARM and Intel doing two different things. > Intel did at least contribute to the perf tool in support for their > BIG.little/hybrid, so that's why the semantics match their approach. I appreciate that, and I agree that from the Arm side we haven't been as engaged with userspace on this front (please understand I'm the messenger here, this is something I've repeatedly asked for within Arm). Regardless, I don't think that changes the substance of the bug, which is that we're converting named-pmu events into entirely different PERF_TYPE_HARDWARE events. I agree that expanding plain legacy event names to a set of PMU-tagetted legacy events makes sense (and even for Arm, that's the right thing to do, IMO). If I ask for 'cycles' and that gets expanded to multiple legacy cycles events that target specific CPU PMUs, that's good. The thing that doesn't make sense here is converting named-pmu events into egacy events. If I ask for 'apple_firestorm_pmu/cycles/', that should be the 'cycles' event in the apple_firestorm_pmu's event namespace, and *shouldn't* be converted to a (potentially semantically different) PERF_TYPE_HARDWARE event, even if that's targetted towards the apple_firestorm_pmu. I think that should be true for *any* PMU, whether thats an arm/x86/whatever CPU PMU or a system PMU. > > > Presumably the expectation was that by advertising a cycles event, presumably > > > in sysfs, then this is what would be matched. Yes. That's how this has always worked prior to the changes Marc referenced. Note that this can *also* be expaned to events from json databases, but was *never* previously silently converted to a PERF_TYPE_HARDWARE event. Please note that the events in sysfs are *namespaced* to the PMU (specifically, when using that PMU's dynamic type); they are not necessarily the same as legacy events (though they may have similar or matching names in some cases), they may be semantically distinct from the legacy events even if the names match, and it is incorrect to conflate the two. > > I expect that if I ask for ${pmu}/${event}/, that PMU is used, and the event > > *in that PMU's namespace* is used. Overriding that breaks long-established > > practice and provides users with no recourse to get the behavioru they expect > > (and previosuly had). > > On ARM but not Intel. As above, I don't think the CPU architecture matters here for the case that I'm saying is broken. I think that regardless of CPU architecture (or for any non-CPU PMU) it is semantically incorrect to convert a named-pmu event to a legacy event. > > I do think that (regardless of whther this was the sematnic you intended) > > silently overriding events with legacy events is a bug, and one we should fix. > > As I mentioned in another reply, just because the events have the same name > > does not mean that they are semantically the same, so we're liable to give > > people the wrong numbers anyhow. > > > > Can we fix this? > > So I'd like to fix this, some things from various conversations: > > 1) we lack testing. Our testing relies on the sysfs of the machine > being run on, which is better than nothing. I think ideally we'd have > a collection of zipped up sysfs directories and then we could have a > test that asserts on ARM you get the behavior you want. I agree we lack testing, and I'd be happy to help here going forwards, though I don't think this is a prerequisite for fixing this issue. > 2) for RISC-V they want to make the legacy event matching something in > user land to simplify the PMU driver. Ok; I see how this might be related, but it doesn't sound like a prerequisite for fixing this issue -- there are plenty of people in this thread who can test. > 3) I'd like to get rid of the PMU json interface. My idea is to > convert json events/metrics into sysfs style files, zip these up and > then link them into the perf binary. On Intel the json is 70% of the > binary (7MB out of 10MB) and we may get this down to 3MB with this > approach. The json lookup would need to incorporate the cpuid matching > that currently exists. When we look up an event I'd like the approach > to be like unionfs with a specified but configurable order. Users > could provide directories of their own events/metrics for various > PMUs, and then this approach could be used to help with (1). I can see how that might interact with whatever changes we make to fix this issue, but this seems like a future aspiration, and not a prerequisite for fixing the existing functional regression. > Those proposals are not something to add as a -rc fix, so what I think > you're asking for here is a "if ARM" fix somewhere in the event > parsing. That's of course possible but it will cause problems if you > did say: > > perf stat -e arm_pmu/LLC-load-misses/ ... As above, I do not think this is an arm-specific issue, we're just the canary in the coalmine. Please note that: perf stat -e arm_pmu/LLC-load-misses/ ... ... would never have worked previously. No arm_pmu instances have a "LLC-load-misses" event in their event namespaces, and we don't have any userspace file mapping that event. That said, If I really wanted that legacy event, I'd have asked for it bare, e.g. perf stat -e LLC-load-misses ... and we're in agreement that it's sensible to expand this to multiple PERF_TYPE_HARDWARE events targeting the individual CPU PMUs. So I see no need to do anything to have magic for 'arm_pmu/LLC-load-misses/'. > as I doubt the PMU driver is advertising this legacy event in sysfs > and the "if ARM" logic would presumably be trying to disable legacy > events in the term list for the ARM PMU. > > Given all of this, is anything actually broken and needing a fix for 6.7? There is absolutely a bug that needs to be fixed here (and needs to be backported to stable so that it gets picked up by distributions). Thanks, Mark.