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Wed, 22 Nov 2023 11:04:35 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 22 Nov 2023 11:04:35 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 22 Nov 2023 11:04:35 -0600 Received: from [172.24.227.94] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AMH4Vqc124276; Wed, 22 Nov 2023 11:04:32 -0600 Message-ID: <522e57a5-20bb-48c4-ac55-15e92ad1a6e2@ti.com> Date: Wed, 22 Nov 2023 22:34:31 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] dt-bindings: dma: ti: k3-*: Add descriptions for register regions To: Krzysztof Kozlowski , Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , References: <20231122154238.815781-1-vigneshr@ti.com> <20231122154238.815781-2-vigneshr@ti.com> Content-Language: en-US From: Vignesh Raghavendra In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 22 Nov 2023 09:05:16 -0800 (PST) On 22/11/23 21:49, Krzysztof Kozlowski wrote: > On 22/11/2023 16:42, Vignesh Raghavendra wrote: >> In preparation for introducing more register regions, add description >> for existing register regions so that its easier to map reg-names to >> that of SoC Documentations/TRMs. >> >> Signed-off-by: Vignesh Raghavendra >> --- >> .../devicetree/bindings/dma/ti/k3-bcdma.yaml | 26 +++++++++++-------- >> .../devicetree/bindings/dma/ti/k3-pktdma.yaml | 6 ++++- >> .../devicetree/bindings/dma/ti/k3-udma.yaml | 5 +++- >> 3 files changed, 24 insertions(+), 13 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml b/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml >> index 4ca300a42a99..b5444800b036 100644 >> --- a/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml >> +++ b/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml >> @@ -35,14 +35,6 @@ properties: >> - ti,am64-dmss-bcdma >> - ti,j721s2-dmss-bcdma-csi >> >> - reg: >> - minItems: 3 >> - maxItems: 5 >> - >> - reg-names: >> - minItems: 3 >> - maxItems: 5 > > Why do you remove properties from top-level? You shouldn't. We expect > there to have widest constrains. This is not explained in commit msg and > really not justified looking at further diff hunks. > Sorry, I didn't realize having top-level constraints is a requirement and thought individual compatibles enforcing that actual constraints is sufficient. Will add these back in v3. > Best regards, > Krzysztof > -- Regards Vignesh