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Message-ID: <ebed123a-f952-4269-bf2c-0c0cd7d6e049@linaro.org>
Date:   Wed, 22 Nov 2023 18:18:44 +0100
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Subject: Re: [PATCH 4/6] arm64: dts: qcom: sm6115: align mem timer size cells
 with bindings
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20231111164229.63803-1-krzysztof.kozlowski@linaro.org>
 <20231111164229.63803-4-krzysztof.kozlowski@linaro.org>
From:   Konrad Dybcio <konrad.dybcio@linaro.org>
In-Reply-To: <20231111164229.63803-4-krzysztof.kozlowski@linaro.org>
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On 11/11/23 17:42, Krzysztof Kozlowski wrote:
> Commit 70d1e09ebf19 ("arm64: dts: qcom: sm6115: Use 64 bit addressing")
> converted all addresses to 64-bit addressing, but the ARMv7 memory
> mapped architected timer bindings expect sizes up to 32-bit.  Keep
> 64-bit addressing but change size of memory mapping to 32-bit
> (size-cells=1) and adjust the ranges to match this.
> 
> This fixes dtbs_check warnings like:
> 
>    sm6115p-lenovo-j606f.dtb: timer@f120000: #size-cells:0:0: 1 was expected
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> ---
> 
> I hope I got the ranges right. Not tested on hardware.
> ---
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad