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Date:   Thu, 23 Nov 2023 08:00:04 +0200
From:   Mika Westerberg <mika.westerberg@linux.intel.com>
To:     Mario Limonciello <mario.limonciello@amd.com>
Cc:     Sanath S <Sanath.S@amd.com>, andreas.noever@gmail.com,
        michael.jamet@intel.com, YehezkelShB@gmail.com,
        linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
        stable@vger.kernel.org
Subject: Re: [Patch v2] thunderbolt: Add quirk to reset downstream port
Message-ID: <20231123060004.GA1074920@black.fi.intel.com>
References: <20231122050639.19651-1-Sanath.S@amd.com>
 <20231122060316.GT1074920@black.fi.intel.com>
 <95ceae27-f88d-4915-870a-36cf9418f244@amd.com>
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On Wed, Nov 22, 2023 at 09:43:55AM -0600, Mario Limonciello wrote:
> On 11/22/2023 00:03, Mika Westerberg wrote:
> > Hi,
> > 
> > On Wed, Nov 22, 2023 at 10:36:39AM +0530, Sanath S wrote:
> > > Boot firmware on AMD's Yellow Carp and Pink Sardine allocates
> > > very minimal buses for PCIe downstream ports. This results in
> > > failure to extend the daisy chain.
> > > 
> > > Add quirk to reset the downstream port to help reset the topology
> > > created by boot firmware.
> > 
> > But this resets the USB4 side of ports, how does this help with the PCIe
> > side? Or this also resets the PCIe side? Please add this information to
> > the changelog too.
> 
> IIUC the PCIe side will be implicitly reset as well.
> 
> > 
> > I suppose it is not possible to fix the boot firmware?
> 
> It's a really difficult case to make with firmware team.  Windows and Linux
> have a different behavior here.  The Windows CM doesn't take the existing
> tunnels from firmware and instead always resets them.
> So Windows "isn't affected" by this problem.
> 
> Furthermore there are already lots of systems out "in the wild" as these are
> already both production silicon with shipping OEM products.

Yeah that's what I was afraid :( Okay we've been there before so let's
work it around in the kernel then.