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[23.128.96.38]) by mx.google.com with ESMTPS id u4-20020a92ccc4000000b003575089fc89si508833ilq.171.2023.11.23.06.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 06:01:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id C59A483212A5; Thu, 23 Nov 2023 06:01:13 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345657AbjKWOA6 (ORCPT + 99 others); Thu, 23 Nov 2023 09:00:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345636AbjKWOA4 (ORCPT ); Thu, 23 Nov 2023 09:00:56 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 551C3B9; Thu, 23 Nov 2023 06:01:03 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7BE811063; Thu, 23 Nov 2023 06:01:49 -0800 (PST) Received: from bogus (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B64253F6C4; Thu, 23 Nov 2023 06:01:00 -0800 (PST) Date: Thu, 23 Nov 2023 14:00:58 +0000 From: Sudeep Holla To: Sumit Gupta Cc: , , , Sudeep Holla , , , , , , , , , , , , , Subject: Re: [Patch v7] ACPI: processor: reduce CPUFREQ thermal reduction pctg for Tegra241 Message-ID: References: <20231123121433.12089-1-sumitg@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231123121433.12089-1-sumitg@nvidia.com> X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Thu, 23 Nov 2023 06:01:14 -0800 (PST) On Thu, Nov 23, 2023 at 05:44:33PM +0530, Sumit Gupta wrote: > From: Srikar Srimath Tirumala > > Current implementation of processor_thermal performs software throttling > in fixed steps of "20%" which can be too coarse for some platforms. > We observed some performance gain after reducing the throttle percentage. > Change the CPUFREQ thermal reduction percentage and maximum thermal steps > to be configurable. Also, update the default values of both for Nvidia > Tegra241 (Grace) SoC. The thermal reduction percentage is reduced to "5%" > and accordingly the maximum number of thermal steps are increased as they > are derived from the reduction percentage. > > Signed-off-by: Srikar Srimath Tirumala > Co-developed-by: Sumit Gupta > Signed-off-by: Sumit Gupta > --- > > Sending this patch separately as the other patch in the series is > applied by Rafael in v6[1]. Revision history before this version is > in the cover letter of v6[1]. > > Please review and provide ACK if looks fine. > For arm64 specific changes(a minor nit below though), Acked-by: Sudeep Holla [...] > diff --git a/drivers/acpi/arm64/thermal_cpufreq.c b/drivers/acpi/arm64/thermal_cpufreq.c > new file mode 100644 > index 000000000000..d524f2cd6044 > --- /dev/null > +++ b/drivers/acpi/arm64/thermal_cpufreq.c > @@ -0,0 +1,20 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +#include > + > +#include "../internal.h" > + > +#define SMCCC_SOC_ID_T241 0x036b0241 > + [nit] We really need to find better place to define this globally and not locally at each usage site like this. We already have it in GICv3 driver. But that can come as a cleanup later if it causes issue for merging this change. -- Regards, Sudeep