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Date:   Thu, 23 Nov 2023 14:45:59 +0000
From:   Conor Dooley <conor.dooley@microchip.com>
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Subject: Re: [PATCH v4 07/13] RISC-V: Move T-Head PMU to CPU feature
 alternative framework
Message-ID: <20231123-snub-headdress-23a80f001ccd@wendy>
References: <20231122121235.827122-1-peterlin@andestech.com>
 <20231122121235.827122-8-peterlin@andestech.com>
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>  drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----

> +config THEAD_CUSTOM_PMU
> +	bool "T-Head custom PMU support"
> +	depends on RISCV_ALTERNATIVE && RISCV_PMU_SBI
> +	default y
> +	help
> +	  The T-Head C9xx cores implement a PMU overflow extension very
> +	  similar to the core SSCOFPMF extension.
> +
> +	  This will patch the overflow CSR and handle the non-standard
> +	  behaviour via the regular SBI PMU driver and interface.
> +
> +	  If you don't know what to do here, say "Y".

This is a < 20 line diff to the pmu driver, is it really worth adding
having config options for these two non standard PMU implementations?

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