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Thu, 23 Nov 2023 10:07:28 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.9.0-alpha0-1234-gac66594aae-fm-20231122.001-gac66594a MIME-Version: 1.0 Message-Id: In-Reply-To: References: <20231122182419.30633-1-fancer.lancer@gmail.com> <20231122182419.30633-2-fancer.lancer@gmail.com> <8ca730b9-fa8c-46ea-bdc5-158da0f29c3a@app.fastmail.com> Date: Thu, 23 Nov 2023 15:07:09 +0000 From: "Jiaxun Yang" To: "Thomas Bogendoerfer" Cc: "Serge Semin" , "Arnd Bergmann" , "Andrew Morton" , "Mike Rapoport" , "Matthew Wilcox" , "Tiezhu Yang" , "Huacai Chen" , "Yinglu Yang" , "Alexey Malahov" , "Aleksandar Rikalo" , "Aleksandar Rikalo" , "Dragan Mladjenovic" , "Chao-ying Fu" , "Marc Zyngier" , "linux-mips@vger.kernel.org" , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/7] mips: dmi: Fix early remap on MIPS32 Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 23 Nov 2023 07:07:47 -0800 (PST) =E5=9C=A82023=E5=B9=B411=E6=9C=8823=E6=97=A5=E5=8D=81=E4=B8=80=E6=9C=88 = =E4=B8=8B=E5=8D=8812:29=EF=BC=8CThomas Bogendoerfer=E5=86=99=E9=81=93=EF= =BC=9A > On Thu, Nov 23, 2023 at 12:13:11PM +0000, Jiaxun Yang wrote: >> > Ok. Thanks for the heads up. I'll fix the patch to be using ioremap= () >> > in v2. ioremap_uc() is just an macro-alias of ioremap() on MIPS. >>=20 >> Perhaps we need to fix ioremap_cache so it can give a KSEG1 address? > > KSEG0 ? Ah yes it's KSEG0. > >> AFAIK for Loongson DMI is located at cached memory so using ioremap_uc >> blindly will cause inconsistency. > > why ? Firmware sometimes does not flush those tables from cache back to memory. For Loongson systems (as well as most MTI systems) cache is enabled by firmware. Thanks. > > Thomas. > > --=20 > Crap can work. Given enough thrust pigs will fly, but it's not necessa= rily a > good idea. [ RFC1925, 2= .3 ] --=20 - Jiaxun