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From:   Alexander Stein <alexander.stein@ew.tq-group.com>
To:     netdev@vger.kernel.org, Heiko Schocher <heiko.schocher@gmail.com>,
        hs@denx.de
Cc:     Clark Wang <xiaoning.wang@nxp.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        NXP Linux Team <linux-imx@nxp.com>,
        Paolo Abeni <pabeni@redhat.com>,
        Shenwei Wang <shenwei.wang@nxp.com>,
        Wei Fang <wei.fang@nxp.com>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] net: fec: fix probing of fec1 when fec0 is not probed yet
Date:   Thu, 23 Nov 2023 16:42:35 +0100
Message-ID: <2305704.ElGaqSPkdT@steina-w>
Organization: TQ-Systems GmbH
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References: <20231123132744.62519-1-hs@denx.de> <5992842.lOV4Wx5bFT@steina-w> <1af63dea-e333-cef7-2bc6-bbf4eb8c3881@denx.de>
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Hello Heiko,

Am Donnerstag, 23. November 2023, 16:26:18 CET schrieb Heiko Schocher:
> Hello Alexander,
>=20
> On 23.11.23 16:11, Alexander Stein wrote:
> > Hello Heiko,
> >=20
> > Am Donnerstag, 23. November 2023, 14:27:43 CET schrieb Heiko Schocher:
> >> it is possible that fec1 is probed before fec0. On SoCs
> >> with FEC_QUIRK_SINGLE_MDIO set (which means fec1 uses mii
> >> from fec0) init of mii fails for fec1 when fec0 is not yet
> >> probed, as fec0 setups mii bus. In this case fec_enet_mii_init
> >> for fec1 returns with -ENODEV, and so fec1 never comes up.
> >>=20
> >> Return here with -EPROBE_DEFER so interface gets later
> >> probed again.
> >>=20
> >> Found this on imx8qxp based board, using 2 ethernet interfaces,
> >> and from time to time, fec1 interface came not up.
> >=20
> > But FEC_QUIRK_SINGLE_MDIO is only set for imx28. How is this related to
> > imx8qxp?
>=20
> Ah, yes ... customer uses NXP based kernel there is:
>=20
>         /* board only enable one mii bus in default */
>         if (!of_get_property(np, "fsl,mii-exclusive", NULL))
>                 fep->quirks |=3D FEC_QUIRK_SINGLE_MDIO;
>=20
> which is missing in mainline... nevertheless patch fixes a problem
> with boards having quirk FEC_QUIRK_SINGLE_MDIO set.

But this seems wrong. Apparently fec driver fails if MDIO bus is not (yet)=
=20
available. But 'fsl,mii-exclusive' + FEC_QUIRK_SINGLE_MDIO assumes both=20
interfaces use fec, no? Will this work e.g. on imx8mp if the FEC PHY is=20
attached to STMMAC (EQOS) PHY?

> > Will this also help for imx6ul when fec1 is almost always probed before
> > fec0 due to order of DT nodes?
>=20
> Yep, I think so...  do you have the chance to test such a setup?

I have a board for that. But I'm not able to test at the moment.

Best regards,
Alexander

> bye,
> Heiko
>=20
> > Best regards,
> > Alexander
> >=20
> >> Signed-off-by: Heiko Schocher <hs@denx.de>
> >> ---
> >>=20
> >>  drivers/net/ethernet/freescale/fec_main.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>=20
> >> diff --git a/drivers/net/ethernet/freescale/fec_main.c
> >> b/drivers/net/ethernet/freescale/fec_main.c index
> >> c3b7694a7485..d956f95e7a65 100644
> >> --- a/drivers/net/ethernet/freescale/fec_main.c
> >> +++ b/drivers/net/ethernet/freescale/fec_main.c
> >> @@ -2445,7 +2445,7 @@ static int fec_enet_mii_init(struct platform_dev=
ice
> >> *pdev) mii_cnt++;
> >>=20
> >>  			return 0;
> >>  	=09
> >>  		}
> >>=20
> >> -		return -ENOENT;
> >> +		return -EPROBE_DEFER;
> >>=20
> >>  	}
> >>  =09
> >>  	bus_freq =3D 2500000; /* 2.5MHz by default */


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