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From:   Kevin Xie <kevin.xie@starfivetech.com>
To:     Bjorn Helgaas <bhelgaas@google.com>
CC:     <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <mason.huo@starfivetech.com>, <leyfoon.tan@starfivetech.com>,
        <minda.chen@starfivetech.com>
Subject: [PATCH v1] PCI: Add PCIE_CONFIG_REQUEST_WAIT_MS waiting time value
Date:   Fri, 24 Nov 2023 09:45:08 +0800
Message-ID: <20231124014508.43358-1-kevin.xie@starfivetech.com>
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Add the PCIE_CONFIG_REQUEST_WAIT_MS marco to define the minimum waiting
time between sending the first configuration request to the device and
exit from a conventional reset (or after link training completes).

As described in the conventional reset rules of PCI specifications,
there are two different use cases of the value:

   - With a downstream port that supports link speeds <= 5.0 GT/s,
     the waiting is following exit from a conventional reset.

   - With a downstream port that supports link speeds > 5.0 GT/s,
     the waiting is after link training completes.

Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
---
 drivers/pci/pci.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 5ecbcf041179..4ca8766e546e 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -22,6 +22,13 @@
  */
 #define PCIE_PME_TO_L2_TIMEOUT_US	10000
 
+/*
+ * PCIe r6.0, sec 6.6.1, <Conventional Reset>
+ * Requires a minimum waiting of 100ms before sending a configuration
+ * request to the device.
+ */
+#define PCIE_CONFIG_REQUEST_WAIT_MS	100
+
 extern const unsigned char pcie_link_speed[];
 extern bool pci_early_dump;
 
-- 
2.25.1