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From:   Anup Patel <apatel@ventanamicro.com>
Date:   Fri, 24 Nov 2023 10:35:14 +0530
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Subject: Re: [PATCH v2 7/9] irqchip: Add RISC-V advanced PLIC driver
To:     =?UTF-8?B?6LCiIOazog==?= <xiebo_60@live.com>
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On Fri, Nov 24, 2023 at 8:33=E2=80=AFAM =E8=B0=A2 =E6=B3=A2 <xiebo_60@live.=
com> wrote:
>
> Hello all,
>
>
> I have a question regarding the handling of potential issues during the M=
SI interrupt sending process. It appears that if the APLIC target register'=
s value is modified during the MSI interrupt sending process, it could pote=
ntially lead to MSI interrupt send failures. The code doesn't seem to accou=
nt for this scenario or take appropriate measures.
>
> I am reaching out to seek clarification on whether this situation has bee=
n considered and if there are specific reasons for not addressing it in the=
 code. Your insights into this matter would be highly appreciated.
>
> Thank you for your time, and I look forward to your response.

This has been taken care of in the IMSIC driver in the irq_set_affinity()
because the IMSIC driver manages the re-writing of MSI messages
upon IRQ affinity changes.

Please look at PATCH7 and PATCH8 of the "[PATCH v11 00/14] Linux
RISC-V AIA Support" series.
(Refer, https://www.spinics.net/lists/devicetree/msg643764.html)

Regards,
Anup

>
> Best regards
>
>
>