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From:   Suman Ghosh <sumang@marvell.com>
To:     Sneh Shah <quic_snehshah@quicinc.com>,
        Vinod Koul <vkoul@kernel.org>,
        Bhupesh Sharma <bhupesh.sharma@linaro.org>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
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        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
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        <linux-stm32@st-md-mailman.stormreply.com>,
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CC:     "kernel@quicinc.com" <kernel@quicinc.com>,
        Andrew Halaney <ahalaney@redhat.com>
Subject: RE: [EXT] [PATCH net] net: stmmac: update Rx clk divider for 10M
 SGMII
Thread-Topic: [EXT] [PATCH net] net: stmmac: update Rx clk divider for 10M
 SGMII
Thread-Index: AQHaHpRi2pdYcgZwIkeOKQ40zfMDp7CJA/Sw
Date:   Fri, 24 Nov 2023 06:39:58 +0000
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References: <20231124050818.1221-1-quic_snehshah@quicinc.com>
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Hi Sneh,

>----------------------------------------------------------------------
>SGMII 10MBPS mode needs RX clock divider to avoid drops in Rx.
>Update configure SGMII function with rx clk divider programming.
>
[Suman] You need to add the Fixes tag as well.
>Signed-off-by: Sneh Shah <quic_snehshah@quicinc.com>
>---
> drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>index d3bf42d0fceb..f8c42e91a624 100644
>--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>@@ -34,6 +34,7 @@
> #define RGMII_CONFIG_LOOPBACK_EN		BIT(2)
> #define RGMII_CONFIG_PROG_SWAP			BIT(1)
> #define RGMII_CONFIG_DDR_MODE			BIT(0)
>+#define RGMII_CONFIG_SGMII_CLK_DVDR		GENMASK(18, 10)
>
> /* SDCC_HC_REG_DLL_CONFIG fields */
> #define SDCC_DLL_CONFIG_DLL_RST			BIT(30)
>@@ -617,6 +618,8 @@ static int ethqos_configure_sgmii(struct qcom_ethqos
>*ethqos)
> 	case SPEED_10:
> 		val |=3D ETHQOS_MAC_CTRL_PORT_SEL;
> 		val &=3D ~ETHQOS_MAC_CTRL_SPEED_MODE;
>+		rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR, BIT(10) |
>+			      GENMASK(15, 14), RGMII_IO_MACRO_CONFIG);
> 		break;
> 	}
>
>--
>2.17.1
>