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Message-ID: <46bba00c-00b7-46db-984c-4391f7fc11f6@linaro.org>
Date:   Fri, 24 Nov 2023 09:27:42 +0100
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Subject: Re: [PATCH v2 18/21] MIPS: mobileye: Add EyeQ5 dtsi
Content-Language: en-US
To:     Gregory CLEMENT <gregory.clement@bootlin.com>,
        Paul Burton <paulburton@kernel.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux-mips@vger.kernel.org, Jiaxun Yang <jiaxun.yang@flygoat.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc:     Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>,
        Tawfik Bayouk <tawfik.bayouk@mobileye.com>,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        =?UTF-8?Q?Th=C3=A9o_Lebrun?= <theo.lebrun@bootlin.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>
References: <20231123152639.561231-1-gregory.clement@bootlin.com>
 <20231123152639.561231-19-gregory.clement@bootlin.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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In-Reply-To: <20231123152639.561231-19-gregory.clement@bootlin.com>
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On 23/11/2023 16:26, Gregory CLEMENT wrote:
> Add a device tree include file for the Mobileye EyeQ5 SoC.
> 
> Based on the work of Slava Samsonov <stanislav.samsonov@intel.com>
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---


> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +	};
> +
> +	cpu_intc: interrupt-controller {
> +		compatible = "mti,cpu-interrupt-controller";
> +		interrupt-controller;
> +		#address-cells = <0>;
> +		#interrupt-cells = <1>;
> +	};
> +
> +	gic: interrupt-controller@140000 {

Why do you put MMIO nodes in top-level?

> +		compatible = "mti,gic";
> +		reg = <0x0 0x140000 0x0 0x20000>;
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +
> +		/*
> +		* Declare the interrupt-parent even though the mti,gic
> +		* binding doesn't require it, such that the kernel can
> +		* figure out that cpu_intc is the root interrupt
> +		* controller & should be probed first.
> +		*/
> +		interrupt-parent = <&cpu_intc>;
> +
> +		timer {
> +			compatible = "mti,gic-timer";
> +			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> +			clocks = <&core0_clk>;
> +		};
> +	};
> +
> +	soc: soc {

Are you sure dtbs_check W=1 does not complain? I think you miss here
address.

> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		compatible = "simple-bus";
> +
> +		uart0: serial@800000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0 0x800000 0x0 0x1000>;
> +			reg-io-width = <4>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks  = <&uart_clk>, <&occ_periph>;
> +			clock-names = "uartclk", "apb_pclk";
> +		};
> +
> +		uart1: serial@900000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0 0x900000 0x0 0x1000>;
> +			reg-io-width = <4>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks  = <&uart_clk>, <&occ_periph>;
> +			clock-names = "uartclk", "apb_pclk";
> +		};
> +
> +		uart2: serial@a00000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0 0xa00000 0x0 0x1000>;
> +			reg-io-width = <4>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks  = <&uart_clk>, <&occ_periph>;
> +			clock-names = "uartclk", "apb_pclk";
> +		};
> +
> +		olb: olb@e00000 {
> +			compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd";
> +			reg = <0 0xe00000 0x0 0x400>;
> +			reg-io-width = <4>;
> +		};
> +

Stray blank line.

> +	};
> +};

Best regards,
Krzysztof