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Fri, 24 Nov 2023 09:01:08 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AO917Iu010147 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Nov 2023 09:01:07 GMT Received: from [10.216.4.60] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 24 Nov 2023 01:01:00 -0800 Message-ID: <4fc27dbb-b0aa-437a-a48c-9deea236282d@quicinc.com> Date: Fri, 24 Nov 2023 14:30:56 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v13 05/10] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver Content-Language: en-US To: Johan Hovold CC: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , , , , , , , , , References: <04615205-e380-4719-aff1-f32c26004b14@quicinc.com> <6d4d959c-b155-471b-b13d-f6fda557cfe0@quicinc.com> From: Krishna Kurapati PSSNV In-Reply-To: Content-Type: text/plain; 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Fri, 24 Nov 2023 01:01:52 -0800 (PST) > >> I didn't add missing interrupts on sc8280xp because I see that current >> interrupts present are working fine (I see ADB working and wakeup >> working as well), but the interrupt vector numbers are off by "1" >> between hs specifics and DT (both upstream and downstream). Will sort it >> out and clean that target up later. > > Which interrupt numbers are off by one here? > My bad, this might be the confusion. The HW specifics say: Controller-2, power_event irq: SYS_apcsQgicSPI[812] Vector-number: 843 Usually vector number = 32 + GIC number AFAIK. By that logic, If vector number is 843, GIC_SPI number is 811 which is same as DT. Probably the GIC_SPI number is printed wrong. The DT matches (vector number - 32). Sorry for mentioning that it is wrong. The DT entries are right and it is working on upstream. The missing hs_phy_irq's have been put on the mail thread on this list before. Regards, Krishna, >> [1]: https://patchwork.kernel.org/project/linux-arm-msm/list/?series=803412 > > I took a quick look at the series, and it looks like this will > eventually clean things up a lot. We should probably define a generic > order for the interrupts with the sometimes optional SS interrupts last. > > Side note: It looks like the threading in that series is broken. > Consider using git-send-email for sending series as it takes care of > things like that. > Usually I do git send-email for the whole out folder where the patches are present, but linux-usb list is common to all the patches in that case, even the DT ones. So to avoid that and to send patches to only relavant mailing lists, I did git send email individually on each patch which might have caused this issue. Will make sure this won't happen again. Regards, Krishna,