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Fri, 24 Nov 2023 10:41:16 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AOAfGXG028633 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Nov 2023 10:41:16 GMT Received: from [10.253.33.181] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 24 Nov 2023 02:41:12 -0800 Message-ID: Date: Fri, 24 Nov 2023 18:41:10 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/6] net: phy: at803x: add QCA8084 ethernet phy support Content-Language: en-US To: "Russell King (Oracle)" CC: Andrew Lunn , , , , , , , , , , , , , References: <1eb60a08-f095-421a-bec6-96f39db31c09@lunn.ch> <1d4d7761-6b42-48ec-af40-747cb4b84ca5@lunn.ch> <316fb626-4dc3-4540-9cc4-e45840e36f77@quicinc.com> <1bd2f3a9-3dd1-4c95-b4e5-c9bf2274f271@quicinc.com> From: Jie Luo In-Reply-To: Content-Type: text/plain; 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Fri, 24 Nov 2023 02:41:42 -0800 (PST) On 11/24/2023 5:53 PM, Russell King (Oracle) wrote: > On Fri, Nov 24, 2023 at 05:47:04PM +0800, Jie Luo wrote: >> >> >> On 11/23/2023 8:01 PM, Russell King (Oracle) wrote: >>> On Thu, Nov 23, 2023 at 06:57:59PM +0800, Jie Luo wrote: >>>> On 11/21/2023 7:52 PM, Russell King (Oracle) wrote: >>>>> Ultimately, you will need a way to use inband signalling with Cisco >>>>> SGMII for 10M/100M/1G speeds, and then switch to 2500base-X when >>>>> operating at 2.5G speeds, and that is done via the PHY driver >>>>> updating phydev->interface. >>>>> >>>>> What we do need is some way for the PHY to also tell the PCS/MAC >>>>> whether inband should be used. This is something I keep bringing up >>>>> and now that we have PCS drivers revised to use the value from >>>>> phylink_pcs_neg_mode() _and_ a consistent implementation amongst them >>>>> we can now think about signalling to PCS drivers whether inband mode >>>>> needs to be turned off when switching between modes. >>>> >>>> Yes, we can switch the interface mode according to the current link >>>> speed in the pcs driver. >>>> but the issue is that the phy-mode i specified for the PHYLINK, >>>> if phy-mode is sgmii, the support capability is limited to maximum >>>> capability 1G during the PHYLINK setup and i can't configure it to 2.5G >>>> dynamically, if the phy-mode is 2500base-x, then PHY capability will >>>> be modified to only support 2.5G, other speeds can't be linked up. >>> >>> So you need my patches that add "possible_interfaces" to phylib so you >>> can tell phylink that you will be switching between SGMII and >>> 2500base-X. Please see the RFC posting of those patches I sent >>> yesterday and try them out - you will need to modify your phylib >>> driver to fill in phydev->possible_interfaces. >> >> Your patches work on my board, thanks Russell. > > Please can you reply to the covering email for that series giving your > tested-by? Thanks. > Ok.