Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32;
Message-ID: <1192d91f-11bf-44af-953a-14e08e2b6ca8@quicinc.com>
Date:   Fri, 24 Nov 2023 17:32:37 +0530
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH 1/6] dt-bindings: usb: dwc3: Clean up hs_phy_irq in
 bindings
To:     Johan Hovold <johan@kernel.org>
CC:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Rob Herring <robh+dt@kernel.org>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>, <quic_wcheng@quicinc.com>,
        <linux-arm-msm@vger.kernel.org>, <linux-usb@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <quic_ppratap@quicinc.com>, <quic_jackp@quicinc.com>
References: <20231122191335.3058-1-quic_kriskura@quicinc.com>
 <ZV9dYpTYRXn63tXe@hovoldconsulting.com>
Content-Language: en-US
From:   Krishna Kurapati PSSNV <quic_kriskura@quicinc.com>
In-Reply-To: <ZV9dYpTYRXn63tXe@hovoldconsulting.com>
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 7bit
Precedence: bulk

> 
> Thanks for sorting this out.
> 
> It seems like we have a few combinations of these interrupts and we
> should probably try to define the order for these once and for all and
> update the current devicetrees to match (even if it means adding new
> interrupts in the middle).
> 
> Instead of adding separate compatibles for the controllers without SS
> support, I suggest keeping that interrupt last as an optional one.
> 
> But IIUC we essentially have something like:
> 
> qusb2-:
> 
> 	- const: qusb2_phy
> 	- const: pwr_event
> 	- const: ss_phy_irq	(optional)
> 
> qusb2:
> 
> 	- const: hs_phy_irq
> 	- const: qusb2_phy
> 	- const: pwr_event
> 	- const: ss_phy_irq	(optional)
> 
> qusb2+:
> 
> 	- const: hs_phy_irq
> 	- const: qusb2_phy
> 	- const: dp_hs_phy_irq
> 	- const: dm_hs_phy_irq
> 	- const: pwr_event
> 	- const: ss_phy_irq	(optional)
> 

This combination doesn't exist. So we can skip this one.

> femto-:
> 	- const: dp_hs_phy_irq
> 	- const: dm_hs_phy_irq
> 	- const: pwr_event
> 	- const: ss_phy_irq	(optional)
> 
> femto:
> 	- const: hs_phy_irq
> 	- const: dp_hs_phy_irq
> 	- const: dm_hs_phy_irq
> 	- const: pwr_event
> 	- const: ss_phy_irq	(optional)
> 
> Does this look like it would cover all of our currents SoCs?
> 
> Do all of them have the pwr_event interrupt?
> 
Yes. From whatever targets I was able to find, only one of them didn't 
have the power_event irq. Rest all of them had. I will recheck that 
particular one again.

> Note that DP comes before DM above as that seems like the natural order
> of these (plus before minus).
> 
> Now if the HS interrupt is truly unusable, I guess we can consider
> dropping it throughout and the above becomes just three permutations
> instead, which can even be expressed along the lines of:
> 

Infact, I wanted to do this but since you mentioned before that if HW 
has it, we must describe it, I kept it in. But since this functionality 
is confirmed to be mutually exclusive of qusb2/{dp/dm}, I am aligned to 
skip it in bindings and drop it in DT.

> 	- anyOf:
> 	  - items:
> 	    - const: qusb2_phy
> 	  - items:
> 	    - const: dp_hs_phy_irq
> 	    - const: dm_hs_phy_irq
> 	- const: pwr_event
> 	- const: ss_phy_irq	(optional)
> 

This must cover all cases AFAIK. How about we keep pwr_event also 
optional for time being. The ones I am not able to find also would come 
up under still binding block.

Regards,
Krishna,