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From:   Dario Binacchi <dario.binacchi@amarulasolutions.com>
Date:   Fri, 24 Nov 2023 14:14:06 +0100
Message-ID: <CABGWkvrvaanicdZi2zaSrWHCrcfFt6Zf2RK6X1oRX=kA28ZfBQ@mail.gmail.com>
Subject: Re: [PATCH] powerpc/85xx: Fix typo in code comment
To:     Christophe Leroy <christophe.leroy@csgroup.eu>
Cc:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Kumar Gala <galak@kernel.crashing.org>,
        Michael Ellerman <mpe@ellerman.id.au>,
        Nicholas Piggin <npiggin@gmail.com>,
        =?UTF-8?Q?Pali_Roh=C3=A1r?= <pali@kernel.org>,
        Rob Herring <robh@kernel.org>, Scott Wood <oss@buserror.net>,
        Timur Tabi <timur@freescale.com>,
        Zhicheng Fan <b32736@freescale.com>,
        "linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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On Fri, Nov 24, 2023 at 2:08=E2=80=AFPM Christophe Leroy
<christophe.leroy@csgroup.eu> wrote:
>
>
>
> Le 24/11/2023 =C3=A0 11:02, Dario Binacchi a =C3=A9crit :
> > s/singals/signals/
>
> Is that really worth it to spend time on such a change ?
>
> By sending such a patch, you require people to spend time reviewing your
> patch, then maintainer has to spend time handling your patch.
> Furthermore, as you added a Fixes: tag, LTS maintainers will have to
> spend time handling that too.
>
> Do you really think that this typo is worth a patch ?
>
> This kind of tiny error should be fixed through a more significant patch
> adressing this file. But it is not worth a patch on its own.

It's not the first time I've submitted patches of this kind, and no one has
ever complained before. However, if it has become an issue, I won't do
it anymore.

Thanks and regards,
Dario
>
> Christophe
>
>
> >
> > Fixes: 04e358d896a7 ("powerpc/85xx: Add Quicc Engine support for p1025r=
db")
> > Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
> > ---
> >
> >   arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/p=
latforms/85xx/mpc85xx_rdb.c
> > index ec9f60fbebc7..e0cec670d8db 100644
> > --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> > +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> > @@ -76,7 +76,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
> >                       /* P1025 has pins muxed for QE and other function=
s. To
> >                       * enable QE UEC mode, we need to set bit QE0 for =
UCC1
> >                       * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, =
QE9
> > -                     * and QE12 for QE MII management singals in PMUXC=
R
> > +                     * and QE12 for QE MII management signals in PMUXC=
R
> >                       * register.
> >                       */
> >                               setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_Q=
E(0) |


--=20

Dario Binacchi

Senior Embedded Linux Developer

dario.binacchi@amarulasolutions.com

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