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(unknown [10.0.2.2]) by helios.alatek.com.pl (Postfix) with ESMTPSA id 70DAA2CE00D8; Fri, 24 Nov 2023 20:26:42 +0100 (CET) From: Jan Kuliga To: lizhi.hou@amd.com, brian.xu@amd.com, raj.kumar.rampelli@amd.com, vkoul@kernel.org, michal.simek@amd.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, runtimeca39d@amd.com Cc: Jan Kuliga Subject: [PATCH v3 4/5] dmaengine: xilinx: xdma: Rework xdma_channel_isr() Date: Fri, 24 Nov 2023 20:25:57 +0100 Message-Id: <20231124192558.135004-5-jankul@alatek.krakow.pl> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231124192524.134989-1-jankul@alatek.krakow.pl> References: <20231124192524.134989-1-jankul@alatek.krakow.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Fri, 24 Nov 2023 11:27:14 -0800 (PST) The xdma's channel status register may be read and cleared simultaneously, by accesing it via seperate XDMA_CHAN_STATUS_RC register. Therefore, it is possible to simplify the code by just getting rid of a seperate redundant write. Also, implement the actual status register checking as well. Previously, the cyclic callback would be scheduled regardless of the status register state. Fix it. Signed-off-by: Jan Kuliga --- drivers/dma/xilinx/xdma-regs.h | 2 ++ drivers/dma/xilinx/xdma.c | 16 ++++++++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-reg= s.h index 654c5e41112d..6bf7ae84e452 100644 --- a/drivers/dma/xilinx/xdma-regs.h +++ b/drivers/dma/xilinx/xdma-regs.h @@ -116,6 +116,8 @@ struct xdma_hw_desc { CHAN_CTRL_IE_WRITE_ERROR | \ CHAN_CTRL_IE_DESC_ERROR) =20 +#define XDMA_CHAN_STATUS_MASK CHAN_CTRL_START + /* bits of the channel interrupt enable mask */ #define CHAN_IM_DESC_ERROR BIT(19) #define CHAN_IM_READ_ERROR BIT(9) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index b8de15e3dcfc..de4615bd4ee5 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -814,15 +814,15 @@ static irqreturn_t xdma_channel_isr(int irq, void *= dev_id) =20 desc->completed_desc_num +=3D complete_desc_num; =20 - if (desc->cyclic) { - ret =3D regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_STATUS, - &st); - if (ret) - goto out; - - regmap_write(xdev->rmap, xchan->base + XDMA_CHAN_STATUS, st); + /* clear-on-read the status register */ + ret =3D regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_STATUS_RC, &st)= ; + if (ret) + goto out; =20 - vchan_cyclic_callback(vd); + if (desc->cyclic) { + st &=3D XDMA_CHAN_STATUS_MASK; + if (st & CHAN_CTRL_IE_DESC_COMPLETED) + vchan_cyclic_callback(vd); goto out; } =20 --=20 2.34.1