Received: by 2002:a05:7412:419a:b0:f3:1519:9f41 with SMTP id i26csp2488005rdh; Sun, 26 Nov 2023 08:05:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IHivMoHGNWjtj3epLg1cL4ll5IdokTWPFuLjX+XQiW5zNstU5qTJyb2cbpszOSa+wgazydg X-Received: by 2002:a17:90b:3e85:b0:280:29d0:2c6e with SMTP id rj5-20020a17090b3e8500b0028029d02c6emr10669476pjb.11.1701014701620; Sun, 26 Nov 2023 08:05:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701014701; cv=none; d=google.com; s=arc-20160816; b=GWAoc5qddLtE/ic5T/cgUNabHkA8iHOPJ1zECaaND815FBXsTHNYaTG4Tvm6ACNyjx V3a4szyIm8IqT2d3iWB1ltuuFvdtfQ9hO/kGKfB93hI8qJNlut1mAMQxL5y+iHc5vplx aFEOngmYpqpJ4+9UhNxFbbzdpLTPNe0TW5YC827wYSWAFxwoLyNiQmHmxgfmIi7GLy8n 8snWsxgq9qwgLc3kfhmG1WK9V7BuRdgNrpijYnc6eGJvcCJ4MD0t51mXjVrtpI9bSBcS W2QIi/bPFShqj4g/aNOausy6VO+62IDDaGa+7hCUUcm2/x+kFGGtagp5irFE+7SQGPnj Vf9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:subject:cc:to:from:date :dkim-signature; bh=K5iQFGwNU83ceIyMQhE15FBUBpydTWW49jPwJ7QvStw=; fh=DhlKcN42/Y0EQUk8QEhJ5In4kaJR7V/XW0xZflU74Nk=; b=tgPBZkG28VGppT9Lga3V7DFK/hmzBeklP7qT2qvwvKTu9w7QTpmAvlvFkI9u1F+ueo e2DkMfmp15p+wNFUy64JZBm9HSxsWCyivFcD3auB0BjluydPVl5lE/rahW4zKwmlz45L 886UykD9m7wh4ZE7nqCpGcjHC2xHV5VOFUhEHPODyBpdFMSXsIF0rmoFps8yDDuhNo51 YZF4xUlGJ6fF3pBHTu0K0qN0MvVWY8W2kDj87AGWx0gQjfAggVmlJ0NS76svQStgJbUI zprcY19RvB9nZHZw9WreSMvRXwl1qCgw1wpFoL0n3+0K96KIy/yC9xkw5fbEuNmGYIHT WpGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=MPCc7s3s; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id pq9-20020a17090b3d8900b00285c4fd2ff0si823732pjb.116.2023.11.26.08.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 08:05:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=MPCc7s3s; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 273CD8061B62; Sun, 26 Nov 2023 08:05:00 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230456AbjKZQEp (ORCPT + 99 others); Sun, 26 Nov 2023 11:04:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230447AbjKZQEm (ORCPT ); Sun, 26 Nov 2023 11:04:42 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD100137 for ; Sun, 26 Nov 2023 08:04:48 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4FACEC433C7; Sun, 26 Nov 2023 16:04:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701014688; bh=juZpsIMH+zxndA5/oqXyf6KAF1d5Vbdex0YVpHNxFtg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=MPCc7s3sMuYrw2qSU3ehirBXCceb+Zc90kY3gwhzjjR+P0ylUyt5udZAKW7GoOy9M wGtg5u2BuYdWwoHbXpTtF1Wu8E4O/Z9S72LP0R4Z0zmHYOSbAeCEpuPF8HSDtfYNZr YnPROqMvDbjjS4XIZmBohZBtm58uHVUfM1RCBjtkVCNTNJ8srAqkVFtDR45d6ErW/I Kz7fWIExR/f2eHHVsj7ts8L7x5Bepurm/ivk0hso233j7Y54y8r4CCpFSzRHpoNPW8 Wv49cTpyWZsBGMoQhAqcNAPFnVG2SsxfSt8sahOiz8q3b4CcHVVKg2UPZzQtt+Kvfk /rxGOnAMw1U9w== Date: Sun, 26 Nov 2023 16:04:38 +0000 From: Jonathan Cameron To: Conor Dooley Cc: Krzysztof Kozlowski , marius.cristea@microchip.com, lars@metafoo.de, robh+dt@kernel.org, jdelvare@suse.com, linux@roeck-us.net, linux-hwmon@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/2] dt-bindings: iio: adc: adding support for PAC193X Message-ID: <20231126160438.01ff57d7@jic23-huawei> In-Reply-To: <20231126-nineteen-clumsy-701ac4145ba8@spud> References: <20231115134453.6656-1-marius.cristea@microchip.com> <20231115134453.6656-2-marius.cristea@microchip.com> <20231116-channel-variety-cc7c262924ad@squawk> <20231125194754.304523e6@jic23-huawei> <20231126-nineteen-clumsy-701ac4145ba8@spud> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Sun, 26 Nov 2023 08:05:00 -0800 (PST) On Sun, 26 Nov 2023 11:24:56 +0000 Conor Dooley wrote: > On Sat, Nov 25, 2023 at 07:47:54PM +0000, Jonathan Cameron wrote: > > On Thu, 16 Nov 2023 18:21:33 +0000 > > Conor Dooley wrote: > > > On Thu, Nov 16, 2023 at 04:01:43PM +0100, Krzysztof Kozlowski wrote: > > > > On 15/11/2023 14:44, marius.cristea@microchip.com wrote: > > > > > From: Marius Cristea > > > > > > +patternProperties: > > > > > + "^channel@[1-4]+$": > > > > > + type: object > > > > > + $ref: adc.yaml > > > > > + description: Represents the external channels which are connected to the ADC. > > > > > + > > > > > + properties: > > > > > + reg: > > > > > + items: > > > > > + minimum: 1 > > > > > + maximum: 4 > > > > > + > > > > > + shunt-resistor-micro-ohms: > > > > > + description: | > > > > > + Value in micro Ohms of the shunt resistor connected between > > > > > + the SENSE+ and SENSE- inputs, across which the current is measured. Value > > > > > + is needed to compute the scaling of the measured current. > > > > > + > > > > > + required: > > > > > + - reg > > > > > + - shunt-resistor-micro-ohms > > > > > + > > > > > + unevaluatedProperties: false > > > > > + > > > > > +required: > > > > > + - compatible > > > > > + - reg > > > > > + - "#address-cells" > > > > > + - "#size-cells" > > > > > + > > > > > +allOf: > > > > > + - if: > > > > > + properties: > > > > > + compatible: > > > > > + contains: > > > > > + const: interrupts > > > > > > > > > > > > I don't understand what do you want to say here. I am also 100% sure you > > > > did not test it on a real case (maybe example passes but nothing more). > > > > > > As far as I understand, the same pin on the device is used for both an > > > output or an input depending on the configuration. As an input, it is > > > the "slow-io" control, and as an output it is an interrupt. > > > I think Marius is trying to convey that either this pin can be in > > > exclusively one state or another. > > > > > > _However_ I am not sure that that is really the right thing to do - they > > > might well be mutually exclusive modes, but I think the decision can be > > > made at runtime, rather than at devicetree creation time. Say for > > > example the GPIO controller this is connected to is capable of acting as > > > an interrupt controller. Unless I am misunderstanding the runtime > > > configurability of this hardware, I think it is possible to actually > > > provide a "slow-io-gpios" and an interrupt property & let the operating > > > system decide at runtime which mode it wants to work in. > > > > I'll admit I've long forgotten what was going on here, but based just on > > this bit of text I agree. There is nothing 'stopping' us having a pin > > uses as either / or / both interrupt and gpio. > > > > It'll be a bit messy to support in the driver as IIRC there are some sanity > > checks that limit combinations on IRQs and output GPIOS. Can't remember > > how bad the dance to navigate it safely is. > > > > First version I'd just say pick one option if both are provided and > > don't support configuring it at runtime. > > Just to be clear, you are suggesting having the > "microchip,slow-io-gpios" and "interrupts" properties in the binding, > but the driver will just (for example) put that pin into alert mode > always & leave it there? Yes. > If that is what you are suggesting, that seems pragmatic to me. If a use case to do something else comes along later, then we can be smarter, but I'd like to keep it simple initially at least. Jonathan > > Cheers, > Conor. >