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Sun, 26 Nov 2023 19:18:35 -0800 (PST) From: Barry Song <21cnbao@gmail.com> X-Google-Original-From: Barry Song To: ryan.roberts@arm.com Cc: akpm@linux-foundation.org, andreyknvl@gmail.com, anshuman.khandual@arm.com, ardb@kernel.org, catalin.marinas@arm.com, david@redhat.com, dvyukov@google.com, glider@google.com, james.morse@arm.com, jhubbard@nvidia.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, mark.rutland@arm.com, maz@kernel.org, oliver.upton@linux.dev, ryabinin.a.a@gmail.com, suzuki.poulose@arm.com, vincenzo.frascino@arm.com, wangkefeng.wang@huawei.com, will@kernel.org, willy@infradead.org, yuzenghui@huawei.com, yuzhao@google.com, ziy@nvidia.com Subject: Re: [PATCH v2 00/14] Transparent Contiguous PTEs for User Mappings Date: Mon, 27 Nov 2023 16:18:13 +1300 Message-Id: <20231127031813.5576-1-v-songbaohua@oppo.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231115163018.1303287-1-ryan.roberts@arm.com> References: <20231115163018.1303287-1-ryan.roberts@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Sun, 26 Nov 2023 19:18:45 -0800 (PST) > Ryan Roberts (14): > mm: Batch-copy PTE ranges during fork() > arm64/mm: set_pte(): New layer to manage contig bit > arm64/mm: set_ptes()/set_pte_at(): New layer to manage contig bit > arm64/mm: pte_clear(): New layer to manage contig bit > arm64/mm: ptep_get_and_clear(): New layer to manage contig bit > arm64/mm: ptep_test_and_clear_young(): New layer to manage contig bit > arm64/mm: ptep_clear_flush_young(): New layer to manage contig bit > arm64/mm: ptep_set_wrprotect(): New layer to manage contig bit > arm64/mm: ptep_set_access_flags(): New layer to manage contig bit > arm64/mm: ptep_get(): New layer to manage contig bit > arm64/mm: Split __flush_tlb_range() to elide trailing DSB > arm64/mm: Wire up PTE_CONT for user mappings > arm64/mm: Implement ptep_set_wrprotects() to optimize fork() > arm64/mm: Add ptep_get_and_clear_full() to optimize process teardown Hi Ryan, Not quite sure if I missed something, are we splitting/unfolding CONTPTES in the below cases 1. madvise(MADV_DONTNEED) on a part of basepages on a CONTPTE large folio 2. vma split in a large folio due to various reasons such as mprotect, munmap, mlock etc. 3. try_to_unmap_one() to reclaim a folio, ptes are scanned one by one rather than being as a whole. In hardware, we need to make sure CONTPTE follow the rule - always 16 contiguous physical address with CONTPTE set. if one of them run away from the 16 ptes group and PTEs become unconsistent, some terrible errors/faults can happen in HW. for example case0: addr0 PTE - has no CONTPE addr0+4kb PTE - has CONTPTE .... addr0+60kb PTE - has CONTPTE case 1: addr0 PTE - has no CONTPE addr0+4kb PTE - has CONTPTE .... addr0+60kb PTE - has swap Unconsistent 16 PTEs will lead to crash even in the firmware based on our observation. Thanks Barry