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Message-ID: <47c9eb95-ff6a-4432-a7ef-1f3ebf6f593f@quicinc.com>
Date:   Mon, 27 Nov 2023 11:25:34 +0530
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Subject: Re: [PATCH net] net: stmmac: update Rx clk divider for 10M SGMII
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To:     "Russell King (Oracle)" <linux@armlinux.org.uk>
CC:     Vinod Koul <vkoul@kernel.org>,
        Bhupesh Sharma <bhupesh.sharma@linaro.org>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Jose Abreu <joabreu@synopsys.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        <netdev@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <linux-stm32@st-md-mailman.stormreply.com>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <kernel@quicinc.com>,
        Andrew Halaney <ahalaney@redhat.com>
References: <20231124050818.1221-1-quic_snehshah@quicinc.com>
 <ZWBo5EKjkffNOqkQ@shell.armlinux.org.uk>
From:   Sneh Shah <quic_snehshah@quicinc.com>
In-Reply-To: <ZWBo5EKjkffNOqkQ@shell.armlinux.org.uk>
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You are right here for GENMASK(15,14) | BIT(10). I am using this to create a field value.I will switch to FIELD_PREP as that seems like a better way to do this.

This field programming is required only for 10M speed in for SGMII mode. other speeds are agnostic to this field. Hence we are programming it always when SGMII link comes up in 10M mode. init driver data for ethqos is common for sgmii and rgmii. As this fix is specific to SGMII we can't add this to init driver data.

On 11/24/2023 2:42 PM, Russell King (Oracle) wrote:
> On Fri, Nov 24, 2023 at 10:38:18AM +0530, Sneh Shah wrote:
>>  #define RGMII_CONFIG_LOOPBACK_EN		BIT(2)
>>  #define RGMII_CONFIG_PROG_SWAP			BIT(1)
>>  #define RGMII_CONFIG_DDR_MODE			BIT(0)
>> +#define RGMII_CONFIG_SGMII_CLK_DVDR		GENMASK(18, 10)
> 
> So you're saying here that this is a 9 bit field...
> 
>> @@ -617,6 +618,8 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
>>  	case SPEED_10:
>>  		val |= ETHQOS_MAC_CTRL_PORT_SEL;
>>  		val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
>> +		rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR, BIT(10) |
>> +			      GENMASK(15, 14), RGMII_IO_MACRO_CONFIG);
> 
> ... and then you use GENMASK(15,14) | BIT(10) here to set bits in that
> bitfield. If there are multiple bitfields, then these should be defined
> separately and the mask built up.
> 
> I suspect that they aren't, and you're using this to generate a _value_
> that has bits 5, 4, and 0 set for something that really takes a _value_.
> So, FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 0x31) or
> FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 49) would be entirely correct
> here.
> 
> The next concern I have is that you're only doing this for SPEED_10.
> If it needs to be programmed for SPEED_10 to work, and not any of the
> other speeds, isn't this something that can be done at initialisation
> time? If it has to be done depending on the speed, then don't you need
> to do this for each speed with an appropriate value?
>