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Message-ID: <826700de-ed89-4ed9-b225-e0453ecbfd3f@quicinc.com>
Date:   Mon, 27 Nov 2023 14:12:12 +0800
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Subject: Re: [PATCH v6 1/6] net: phy: introduce core support for phy-mode =
 "10g-qxgmii"
To:     Andrew Lunn <andrew@lunn.ch>
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 <f97fd2f0-3e39-4de0-8b1c-f333a0f56a7f@lunn.ch>
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From:   Jie Luo <quic_luoj@quicinc.com>
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On 11/27/2023 1:20 AM, Andrew Lunn wrote:
> On Sun, Nov 26, 2023 at 02:07:27PM +0800, Luo Jie wrote:
>> From: Vladimir Oltean <vladimir.oltean@nxp.com>
>>
>> 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport
>> specification. It uses the same signaling as USXGMII, but it multiplexes
>> 4 ports over the link, resulting in a maximum speed of 2.5G per port.
>>
>> Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean
>> either the single-port USXGMII or the quad-port 10G-QXGMII variant, and
>> they could get away just fine with that thus far. But there is a need to
>> distinguish between the 2 as far as SerDes drivers are concerned.
> 
> Can this is split into two patches?

This patch is a single logical for introducing the mode 10g-qxgmii,
looks it's better to keep it within a single patch.

> 
>>   	switch (interface) {
>>   	case PHY_INTERFACE_MODE_USXGMII:
>> -		caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD;
>> +		caps |= MAC_10000FD | MAC_5000FD;
>> +		fallthrough;
> 
> This change seems to refer to the second paragraph, where as the rest
> of the code is about the first. Or does splitting this cause a bisect
> problem?
> 
> 	Andrew

Since the caps change is related to the new added interface mode
10g-qxgmii, it is reasonable to keep the changes integrated here.