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Message-ID: <f0604c25-87a7-497a-8884-7a779ee7a2f5@quicinc.com>
Date:   Mon, 27 Nov 2023 14:21:46 +0800
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Subject: Re: [PATCH v6 3/6] net: phy: at803x: add QCA8084 ethernet phy support
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To:     Andrew Lunn <andrew@lunn.ch>
CC:     <davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
        <pabeni@redhat.com>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <hkallweit1@gmail.com>, <linux@armlinux.org.uk>, <corbet@lwn.net>,
        <netdev@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <linux-doc@vger.kernel.org>
References: <20231126060732.31764-1-quic_luoj@quicinc.com>
 <20231126060732.31764-4-quic_luoj@quicinc.com>
 <0b22dd51-417c-436d-87ce-7ebc41185860@lunn.ch>
From:   Jie Luo <quic_luoj@quicinc.com>
In-Reply-To: <0b22dd51-417c-436d-87ce-7ebc41185860@lunn.ch>
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On 11/27/2023 1:31 AM, Andrew Lunn wrote:
>> +		/* There are two PCSs available for QCA8084, which support the
>> +		 * following interface modes.
>> +		 *
>> +		 * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all
>> +		 * available 4 ports, which is for all link speeds.
>> +		 *
>> +		 * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the
>> +		 * fourth port, which is only for the link speed 2500M same
>> +		 * as QCA8081.
>> +		 *
>> +		 * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth
>> +		 * port, which is for the link speed 10M, 100M and 1000M same
>> +		 * as QCA8081.
>> +		 */
> 
> How are these 3 modes configured? I don't see any software
> configuration of this in these drivers. Can it only by configured by
> strapping?

The interface mode is passed in the .config_init, which is configured
by the PCS driver, the hardware register is located in the PCS, this
driver will be pushed later.

> 
> I think there should be some validation of the phydev->interface
> mode. Are ports 1-3 set to PHY_INTERFACE_MODE_10G_QXGMII? Is port 4
> interface mode consistent with the strapping?
> 
> 	  Andrew

All ports(1-4) can be PHY_INTERFACE_MODE_10G_QXGMII, if port4 is
connected with PCS0, which will works on sgmii/2500basex mode,
these configuration is controlled by register instead of boot strapping.