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Date:   Mon, 27 Nov 2023 10:39:16 +0000
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Jisheng Zhang <jszhang@kernel.org>
CC:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] riscv: Use asm-generic for {read,write}{bwlq} and their
 relaxed variant
Message-ID: <20231127-swell-garnish-3f2104647aa0@wendy>
References: <20231123142003.1759-1-jszhang@kernel.org>
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On Thu, Nov 23, 2023 at 10:20:03PM +0800, Jisheng Zhang wrote:
> The asm-generic implementation is functionally identical to the riscv
> version.
>=20
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>

This fails to build for nommu:
  /tmp/tmp.ojumpiEgOt/arch/riscv/include/asm/timex.h:20:16: error: implicit=
 declaration of function 'readq_relaxed' [-Werror=3Dimplicit-function-decla=
ration]
  /tmp/tmp.ojumpiEgOt/include/asm-generic/io.h:342:23: error: conflicting t=
ypes for 'readq_relaxed'; have 'u64(const volatile void *)' {aka 'long long=
 unsigned int(const volatile void *)'}

  Cheers,
  Conor.

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