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Mon, 27 Nov 2023 14:36:45 +0000 Message-ID: Date: Mon, 27 Nov 2023 15:36:38 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net v3] net: stmmac: xgmac: Disable FPE MMC interrupts Content-Language: en-US To: Furong Xu <0x1207@gmail.com>, "David S. Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Joao Pinto , Simon Horman CC: , , , , , , Larysa Zaremba References: <20231125060126.2328690-1-0x1207@gmail.com> From: Wojciech Drewek In-Reply-To: <20231125060126.2328690-1-0x1207@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: WA2P291CA0028.POLP291.PROD.OUTLOOK.COM (2603:10a6:1d0:1f::23) To MW4PR11MB5776.namprd11.prod.outlook.com (2603:10b6:303:183::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW4PR11MB5776:EE_|PH8PR11MB6681:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c3846b9-c6f1-4440-673e-08dbef5647ed X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5sjZXVz8BV0b2Xg3KAq/xSfrpsaYtwWTbqII5DWXoGI1PvG2Nk+JywtPZaVBby60VAtRetwMqkwdgSkTvzC5PK7EwBLYXht1BgfkOg0PlI5VA7AOdPPIK0d0TnXxF8FzWHWZZXklT3pGaQEgCNpDj3neziz2zmLWNwhxAiXAL05U5ct701yzHQ7BRFwhvJDAZf9p0hJDOR07epmhC+Rh0VclT6wwru4/6jIaXeee7e49qmlKP5BeLtzTgZb/Z/CfpYSlZsPT1dikWPFcItsuzXQxwAGQ9RVppDxYObmvymnA52pYWkNpXMEektetSZTfrBH0R/hYEO+wJHe175f/YAZu7v/F3OqNSlK23SFPpZj+4nPJ+904tiHGkrNTAZfKcWJTKwLASZesUB4dRJI9EHFuxLESFnnmWoW3CFb04tx7f78duIGQSAvfsUXH4TLbmt2UxoP3oc4xVA5k2GjGJDZQ25bWqUJrIcXyGuV/etx/ksjgOHh/RhjIIswNotDWyP47xlJZCQLTjQjI7T1dP5UkmOfJQ7Y8nPz0o1EoVeHw3vXX9uf2jWj19y0WFok0z2PDmmTJG2j2EqZASuPi6UVnuih/VNYAIRoH/Pc/Bj4Pf3tO+lVfH3uwkxkRV1rMpfe3DCkW95UzdCdlbGbJkrNvf9ormxx8dbvBQuRova4= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW4PR11MB5776.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(366004)(396003)(346002)(136003)(376002)(230922051799003)(186009)(64100799003)(451199024)(1800799012)(107886003)(2616005)(26005)(6506007)(6666004)(6512007)(4326008)(8936002)(82960400001)(8676002)(7416002)(44832011)(31696002)(5660300002)(86362001)(478600001)(6486002)(110136005)(66946007)(66556008)(316002)(66476007)(38100700002)(83380400001)(31686004)(53546011)(921008)(41300700001)(2906002)(36756003)(43740500002)(45980500001);DIR:OUT;SFP:1102; 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Mon, 27 Nov 2023 07:10:42 -0800 (PST) On 25.11.2023 07:01, Furong Xu wrote: > Commit aeb18dd07692 ("net: stmmac: xgmac: Disable MMC interrupts > by default") tries to disable MMC interrupts to avoid a storm of > unhandled interrupts, but leaves the FPE(Frame Preemption) MMC > interrupts enabled, FPE MMC interrupts can cause the same problem. > Now we mask FPE TX and RX interrupts to disable all MMC interrupts. > > Fixes: aeb18dd07692 ("net: stmmac: xgmac: Disable MMC interrupts by default") > Reviewed-by: Larysa Zaremba > Signed-off-by: Furong Xu <0x1207@gmail.com> > --- > Changes in v3: > - Update commit message, thanks Larysa. > - Rename register defines, thanks Serge. > > Changes in v2: > - Update commit message, thanks Wojciech and Andrew. > --- Reviewed-by: Wojciech Drewek > drivers/net/ethernet/stmicro/stmmac/mmc_core.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c > index ea4910ae0921..6a7c1d325c46 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c > +++ b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c > @@ -177,8 +177,10 @@ > #define MMC_XGMAC_RX_DISCARD_OCT_GB 0x1b4 > #define MMC_XGMAC_RX_ALIGN_ERR_PKT 0x1bc > > +#define MMC_XGMAC_TX_FPE_INTR_MASK 0x204 > #define MMC_XGMAC_TX_FPE_FRAG 0x208 > #define MMC_XGMAC_TX_HOLD_REQ 0x20c > +#define MMC_XGMAC_RX_FPE_INTR_MASK 0x224 > #define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR 0x228 > #define MMC_XGMAC_RX_PKT_SMD_ERR 0x22c > #define MMC_XGMAC_RX_PKT_ASSEMBLY_OK 0x230 > @@ -352,6 +354,8 @@ static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr) > { > writel(0x0, mmcaddr + MMC_RX_INTR_MASK); > writel(0x0, mmcaddr + MMC_TX_INTR_MASK); > + writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_TX_FPE_INTR_MASK); > + writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_FPE_INTR_MASK); > writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK); > } >