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Date:   Mon, 27 Nov 2023 08:43:44 -0800
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Subject: Re: [PATCH v3 5/5] dmaengine: xilinx: xdma: Ease dma_pool alignment
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To:     Jan Kuliga <jankul@alatek.krakow.pl>, <brian.xu@amd.com>,
        <raj.kumar.rampelli@amd.com>, <vkoul@kernel.org>,
        <michal.simek@amd.com>, <dmaengine@vger.kernel.org>,
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References: <20231124192524.134989-1-jankul@alatek.krakow.pl>
 <20231124192558.135004-6-jankul@alatek.krakow.pl>
From:   Lizhi Hou <lizhi.hou@amd.com>
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On 11/24/23 11:25, Jan Kuliga wrote:
> According to the XDMA datasheet (PG195), the address of any descriptor
> must be 32 byte aligned. The datasheet also states that a contiguous
> block of descriptors must not cross a 4k address boundary. Therefore,
> it is possible to ease the pressure put on the dma_pool allocator
> just by requiring sufficient alignment and boundary values. Add proper
> macro definition and change the values passed into the
> dma_pool_create().
>
> Signed-off-by: Jan Kuliga <jankul@alatek.krakow.pl>
> ---
>   drivers/dma/xilinx/xdma-regs.h | 7 ++++---
>   drivers/dma/xilinx/xdma.c      | 6 +++---
>   2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-regs.h
> index 6bf7ae84e452..d5cb12e6b8d4 100644
> --- a/drivers/dma/xilinx/xdma-regs.h
> +++ b/drivers/dma/xilinx/xdma-regs.h
> @@ -64,9 +64,10 @@ struct xdma_hw_desc {
>   	__le64		next_desc;
>   };
>   
> -#define XDMA_DESC_SIZE		sizeof(struct xdma_hw_desc)
> -#define XDMA_DESC_BLOCK_SIZE	(XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)
> -#define XDMA_DESC_BLOCK_ALIGN	4096
> +#define XDMA_DESC_SIZE			sizeof(struct xdma_hw_desc)
> +#define XDMA_DESC_BLOCK_SIZE		(XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)
> +#define XDMA_DESC_BLOCK_ALIGN		32
> +#define XDMA_DESC_BLOCK_BOUNDARY	4096
>   
>   /*
>    * Channel registers
> diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c
> index de4615bd4ee5..d32ae93e18b6 100644
> --- a/drivers/dma/xilinx/xdma.c
> +++ b/drivers/dma/xilinx/xdma.c
> @@ -735,9 +735,9 @@ static int xdma_alloc_chan_resources(struct dma_chan *chan)
>   		return -EINVAL;
>   	}
>   
> -	xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan),
> -					       dev, XDMA_DESC_BLOCK_SIZE,
> -					       XDMA_DESC_BLOCK_ALIGN, 0);
> +	xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan), dev,
> +				XDMA_DESC_BLOCK_SIZE, XDMA_DESC_BLOCK_ALIGN,
> +						XDMA_DESC_BLOCK_BOUNDARY);
>   	if (!xdma_chan->desc_pool) {
>   		xdma_err(xdev, "unable to allocate descriptor pool");
>   		return -ENOMEM;

This is probably not needed. The 32 adjacent descriptors here is 1024 
bytes. Defining 4k alignment should be good enough.

Thanks,

Lizhi