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Date:   Mon, 27 Nov 2023 14:22:23 +0100
From:   Andrew Lunn <andrew@lunn.ch>
To:     Jie Luo <quic_luoj@quicinc.com>
Cc:     davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
        pabeni@redhat.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        hkallweit1@gmail.com, linux@armlinux.org.uk, corbet@lwn.net,
        netdev@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org
Subject: Re: [PATCH v6 3/6] net: phy: at803x: add QCA8084 ethernet phy support
Message-ID: <8e4046dd-813c-4766-83fb-c54a700caf31@lunn.ch>
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 <0b22dd51-417c-436d-87ce-7ebc41185860@lunn.ch>
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On Mon, Nov 27, 2023 at 02:21:46PM +0800, Jie Luo wrote:
> 
> 
> On 11/27/2023 1:31 AM, Andrew Lunn wrote:
> > > +		/* There are two PCSs available for QCA8084, which support the
> > > +		 * following interface modes.
> > > +		 *
> > > +		 * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all
> > > +		 * available 4 ports, which is for all link speeds.
> > > +		 *
> > > +		 * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the
> > > +		 * fourth port, which is only for the link speed 2500M same
> > > +		 * as QCA8081.
> > > +		 *
> > > +		 * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth
> > > +		 * port, which is for the link speed 10M, 100M and 1000M same
> > > +		 * as QCA8081.
> > > +		 */
> > 
> > How are these 3 modes configured? I don't see any software
> > configuration of this in these drivers. Can it only by configured by
> > strapping?
> 
> The interface mode is passed in the .config_init, which is configured
> by the PCS driver, the hardware register is located in the PCS, this
> driver will be pushed later.

Is this the same as how the syqca807x works? Can the PCS driver be
shared by these two drivers?

What i don't like at the moment is that we have two driver
developments going on at once for hardware which seems very similar,
but no apparent cooperation?

	Andrew