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X-IronPort-AV: E=McAfee;i="6600,9927,10907"; a="459260235" X-IronPort-AV: E=Sophos;i="6.04,231,1695711600"; d="scan'208";a="459260235" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2023 10:13:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10907"; a="802723886" X-IronPort-AV: E=Sophos;i="6.04,231,1695711600"; d="scan'208";a="802723886" Received: from jdmart2-mobl1.amr.corp.intel.com (HELO [10.212.214.63]) ([10.212.214.63]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2023 10:13:45 -0800 Message-ID: Date: Mon, 27 Nov 2023 10:13:45 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v15 17/23] x86/kexec: Flush cache of TDX private memory Content-Language: en-US To: Kai Huang , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: x86@kernel.org, kirill.shutemov@linux.intel.com, peterz@infradead.org, tony.luck@intel.com, tglx@linutronix.de, bp@alien8.de, mingo@redhat.com, hpa@zytor.com, seanjc@google.com, pbonzini@redhat.com, rafael@kernel.org, david@redhat.com, dan.j.williams@intel.com, len.brown@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, ying.huang@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, nik.borisov@suse.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com References: <2151c68079c1cb837d07bd8015e4ff1f662e1a6e.1699527082.git.kai.huang@intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Mon, 27 Nov 2023 10:13:56 -0800 (PST) On 11/9/23 03:55, Kai Huang wrote: ... > --- a/arch/x86/kernel/reboot.c > +++ b/arch/x86/kernel/reboot.c > @@ -31,6 +31,7 @@ > #include > #include > #include > +#include > > /* > * Power off function, if any > @@ -741,6 +742,20 @@ void native_machine_shutdown(void) > local_irq_disable(); > stop_other_cpus(); > #endif > + /* > + * stop_other_cpus() has flushed all dirty cachelines of TDX > + * private memory on remote cpus. Unlike SME, which does the > + * cache flush on _this_ cpu in the relocate_kernel(), flush > + * the cache for _this_ cpu here. This is because on the > + * platforms with "partial write machine check" erratum the > + * kernel needs to convert all TDX private pages back to normal > + * before booting to the new kernel in kexec(), and the cache > + * flush must be done before that. If the kernel took SME's way, > + * it would have to muck with the relocate_kernel() assembly to > + * do memory conversion. > + */ > + if (platform_tdx_enabled()) > + native_wbinvd(); Why can't the TDX host code just set host_mem_enc_active=1? Sure, you'll end up *using* the SME WBINVD support, but then you don't have two different WBINVD call sites. You also don't have to mess with a single line of assembly.