Received: by 2002:a05:7412:419a:b0:f3:1519:9f41 with SMTP id i26csp3370002rdh; Mon, 27 Nov 2023 12:24:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IG7cTiGzCnN/KvmNpzvxOu1+J5p+pgfn8NEZFQjw/8DMSitHFMEONJoPu7L5jZtnrJhyNrA X-Received: by 2002:a05:6a00:f87:b0:6c6:a139:eabf with SMTP id ct7-20020a056a000f8700b006c6a139eabfmr14421860pfb.3.1701116666467; Mon, 27 Nov 2023 12:24:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701116666; cv=none; d=google.com; s=arc-20160816; b=ptiM8NQEEbwE6PuF/nrviR2lpzOSBd93l/Xbfc/fefhzXJKRKIve1GRHLMbIYgzEPQ +nPxkACQ6BrkfT2Es/DICnAA9WIzpIgPmyhuW7Fft1AW75uH2yRIJHowMC+V2j/HdQ9R AG7/C6OjYb1ayonfSISK0NETRHn/gsOpu5S/7+X+acbNp76b8n/xyzmlznZnYD2S7tbb cees5Ii3rdT9vRqLJv7cMnmycqj+3J1x7A2lqnsXPbwJZQM90IghTGAp4uUqRo6Yw11j Iv1uhKU300z83C6jVuUvS9Nr+r+QD4iWNvKXCRGDxWwjzyISje4bucqf1pkFs1mZ0Tt8 QVVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:to:from; bh=0PBEeBWnipyjt/hHPpjwjysUy9NLs72imShqGvtvQCA=; fh=3z/gW4at6OS98BCTD1uCr4dr/Snb907m0l32nuetVDg=; b=xbPcLkzQgVqx6pvy503LOJ+GL7mUS12p4Dak2b2c9o30AuFxRGI07voxFY/8BOeD+r FcMG7eMjgy6D43Thi8c2u4BqbUrDkXH68n8hEmqU6SVigWBVhuk6ISs0W8cXlhfif2Mo ncQ0y875ITKp0Onju8rcglaOuhvu9MqMTCZT6PMPYnk6braFdzModZj/p7yvSP9LkqmN s8NDl804mj3VSVeiV8RzKwJeES4NYhmIZgqYXzCjPO1yfzShn6hQWZyPusmNkg7ej05l 7zg7YiG5R69YoDEQu5Mt0MNf4gXLs4s2Q3NVKrgx/lx/+Inn3BbC856ZqjSVxC6UvMoT JtQQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id e34-20020a635462000000b005c2791fedb4si10127921pgm.21.2023.11.27.12.24.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 12:24:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 342EC82492A0; Mon, 27 Nov 2023 12:24:23 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231771AbjK0UYH (ORCPT + 99 others); Mon, 27 Nov 2023 15:24:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229527AbjK0UYG (ORCPT ); Mon, 27 Nov 2023 15:24:06 -0500 Received: from mail.andi.de1.cc (mail.andi.de1.cc [IPv6:2a02:c205:3004:2154::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9D581BD; Mon, 27 Nov 2023 12:24:12 -0800 (PST) Received: from p200301077700a9001a3da2fffebfd33a.dip0.t-ipconnect.de ([2003:107:7700:a900:1a3d:a2ff:febf:d33a] helo=aktux) by mail.andi.de1.cc with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1r7i9I-006mnO-M7; Mon, 27 Nov 2023 21:24:08 +0100 Received: from andi by aktux with local (Exim 4.96) (envelope-from ) id 1r7i9I-000bvU-1J; Mon, 27 Nov 2023 21:24:08 +0100 From: Andreas Kemnade To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, andreas@kemnade.info, kristo@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH] dt-bindings: clock: ti: Convert interface.txt to json-schema Date: Mon, 27 Nov 2023 21:23:59 +0100 Message-Id: <20231127202359.145778-1-andreas@kemnade.info> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 27 Nov 2023 12:24:23 -0800 (PST) Convert the OMAP interface clock device tree binding to json-schema and fix up reg property which is optional and taken from parent if not specified. Specify the creator of the original binding as a maintainer. Signed-off-by: Andreas Kemnade --- .../bindings/clock/ti/interface.txt | 57 ------------ .../bindings/clock/ti/ti,interface-clock.yaml | 90 +++++++++++++++++++ 2 files changed, 90 insertions(+), 57 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt create mode 100644 Documentation/devicetree/bindings/clock/ti/ti,interface-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt deleted file mode 100644 index d3eb5ca92a7fe..0000000000000 --- a/Documentation/devicetree/bindings/clock/ti/interface.txt +++ /dev/null @@ -1,57 +0,0 @@ -Binding for Texas Instruments interface clock. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. This clock is -quite much similar to the basic gate-clock [2], however, -it supports a number of additional features, including -companion clock finding (match corresponding functional gate -clock) and hardware autoidle enable / disable. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml - -Required properties: -- compatible : shall be one of: - "ti,omap3-interface-clock" - basic OMAP3 interface clock - "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware - capability for waiting clock to be ready - "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW - handling - "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling - "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling - "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling - "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW - handling -- #clock-cells : from common clock binding; shall be set to 0 -- clocks : link to phandle of parent clock -- reg : base address for the control register - -Optional properties: -- clock-output-names : from common clock binding. -- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0) - -Examples: - aes1_ick: aes1_ick@48004a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x48004a14 0x4>; - ti,bit-shift = <3>; - }; - - cam_ick: cam_ick@48004f10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x48004f10 0x4>; - ti,bit-shift = <0>; - }; - - ssi_ick_3430es2: ssi_ick_3430es2@48004a10 { - #clock-cells = <0>; - compatible = "ti,omap3-ssi-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x48004a10 0x4>; - ti,bit-shift = <0>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/ti,interface-clock.yaml b/Documentation/devicetree/bindings/clock/ti/ti,interface-clock.yaml new file mode 100644 index 0000000000000..48a54caeb3857 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/ti,interface-clock.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,interface-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments interface clock. + +maintainers: + - Tero Kristo + +description: | + This binding uses the common clock binding[1]. This clock is + quite much similar to the basic gate-clock[2], however, + it supports a number of additional features, including + companion clock finding (match corresponding functional gate + clock) and hardware autoidle enable / disable. + + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml + + +properties: + compatible: + enum: + - ti,omap3-interface-clock # basic OMAP3 interface clock + - ti,omap3-no-wait-interface-clock # interface clock which has no hardware + # capability for waiting clock to be ready + - ti,omap3-hsotgusb-interface-clock # interface clock with USB specific HW handling + - ti,omap3-dss-interface-clock # interface clock with DSS specific HW handling + - ti,omap3-ssi-interface-clock # interface clock with SSI specific HW handling + - ti,am35xx-interface-clock # interface clock with AM35xx specific HW handling + - ti,omap2430-interface-clock # interface clock with OMAP2430 specific HW handling + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + reg: + description: + if not specified, value from parent is used + maxItems: 1 + + ti,bit-shift: + description: + bit shift for the bit enabling/disabling the clock + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + +required: + - compatible + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <1>; + + aes1_ick: aes1-ick@48004a14 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + reg = <0x48004a14 0x4>; + ti,bit-shift = <3>; + }; + + cam_ick: cam-ick@48004f10 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ick>; + reg = <0x48004f10 0x4>; + ti,bit-shift = <0>; + }; + + ssi_ick_3430es2: ssi-ick-3430es2@48004a10 { + #clock-cells = <0>; + compatible = "ti,omap3-ssi-interface-clock"; + clocks = <&ssi_l4_ick>; + reg = <0x48004a10 0x4>; + ti,bit-shift = <0>; + }; + }; -- 2.39.2