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References: <20231122-x1e80100-clk-tcsrcc-v1-0-43078c6d6452@linaro.org> <20231122-x1e80100-clk-tcsrcc-v1-2-43078c6d6452@linaro.org>
Subject: Re: [PATCH 2/2] clk: qcom: Add TCSR clock driver for x1e80100
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Abel Vesa <abel.vesa@linaro.org>
To:     Abel Vesa <abel.vesa@linaro.org>, Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Rajendra Nayak <quic_rjendra@quicinc.com>,
        Rob Herring <robh+dt@kernel.org>
Date:   Mon, 27 Nov 2023 15:41:24 -0800
User-Agent: alot/0.10
Precedence: bulk

Quoting Abel Vesa (2023-11-22 05:42:13)
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index ad1acd9b7426..6ed9c89d9070 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -1116,4 +1116,12 @@ config SM_VIDEOCC_8450
>           SM8450 devices.
>           Say Y if you want to support video devices and functionality su=
ch as
>           video encode/decode.
> +
> +config X1E_TCSRCC_80100

Is the config symbol intentionally namespaced for X1E prefix to group
one SoC? Why not X1E80100_TCSRCC then?

> +       tristate "X1E80100 TCSR Clock Controller"
> +       depends on ARM64 || COMPILE_TEST
> +       select QCOM_GDSC
> +       help
> +         Support for the TCSR clock controller on X1E80100 devices.
> +         Say Y if you want to use peripheral devices such as SD/UFS.
>  endif
> diff --git a/drivers/clk/qcom/tcsrcc-x1e80100.c b/drivers/clk/qcom/tcsrcc=
-x1e80100.c
> new file mode 100644
> index 000000000000..2ec142c3d1f9
> --- /dev/null
> +++ b/drivers/clk/qcom/tcsrcc-x1e80100.c
> @@ -0,0 +1,295 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reser=
ved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "common.h"
> +#include "reset.h"
> +
> +enum {
> +       DT_BI_TCXO_PAD,
> +};
> +
> +static struct clk_branch tcsr_edp_clkref_en =3D {
> +       .halt_reg =3D 0x15130,
> +       .halt_check =3D BRANCH_HALT_DELAY,
> +       .clkr =3D {
> +               .enable_reg =3D 0x15130,
> +               .enable_mask =3D BIT(0),
> +               .hw.init =3D &(const struct clk_init_data) {
> +                       .name =3D "tcsr_edp_clkref_en",
> +                       .ops =3D &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch tcsr_pcie_2l_4_clkref_en =3D {
> +       .halt_reg =3D 0x15100,
> +       .halt_check =3D BRANCH_HALT_DELAY,

Why are these all branch halt delay but still have a halt_reg?

> +       .clkr =3D {
> +               .enable_reg =3D 0x15100,
> +               .enable_mask =3D BIT(0),
> +               .hw.init =3D &(struct clk_init_data){

const?

> +                       .name =3D "tcsr_pcie_2l_4_clkref_en",
> +                       .parent_data =3D &(const struct clk_parent_data){
> +                               .index =3D DT_BI_TCXO_PAD,
> +                       },