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Tue, 28 Nov 2023 07:42:12 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.9.0-alpha0-1234-gac66594aae-fm-20231122.001-gac66594a MIME-Version: 1.0 Message-Id: In-Reply-To: References: <20231122182419.30633-2-fancer.lancer@gmail.com> <8ca730b9-fa8c-46ea-bdc5-158da0f29c3a@app.fastmail.com> <245d3985-9085-4be0-8c74-d95d06334584@app.fastmail.com> <3iksuovvsln3cw3xpmjd7f7xixfvwaneu4ok56fnookvyolpco@wrxxew3thgnq> Date: Tue, 28 Nov 2023 13:41:51 +0100 From: "Arnd Bergmann" To: "Serge Semin" , "Jiaxun Yang" Cc: "Thomas Bogendoerfer" , "Andrew Morton" , "Mike Rapoport" , "Matthew Wilcox" , "Tiezhu Yang" , "Huacai Chen" , "Yinglu Yang" , "Alexey Malahov" , "Aleksandar Rikalo" , "Aleksandar Rikalo" , "Dragan Mladjenovic" , "Chao-ying Fu" , "Marc Zyngier" , "linux-mips@vger.kernel.org" , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/7] mips: dmi: Fix early remap on MIPS32 Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 28 Nov 2023 04:42:27 -0800 (PST) On Mon, Nov 27, 2023, at 17:23, Serge Semin wrote: > On Fri, Nov 24, 2023 at 10:03:49PM +0000, Jiaxun Yang wrote: >> =E5=9C=A82023=E5=B9=B411=E6=9C=8824=E6=97=A5=E5=8D=81=E4=B8=80=E6=9C=88= =E4=B8=8B=E5=8D=886:52=EF=BC=8CSerge Semin=E5=86=99=E9=81=93=EF=BC=9A >> > On Thu, Nov 23, 2023 at 05:33:31PM +0000, Jiaxun Yang wrote: >> >>=20 >> [...] >> >> Actually dmi_setup() is called before cpu_cache_init(). >> > >> > To preliminary sum the discussion, indeed there can be issues on the >> > platforms which have DMI initialized on the cached region. Here are >> > several solutions and additional difficulties I think may be caused= by >> > implementing them: >>=20 >> Thanks for such detailed conclusion! >> I'd prefer go solution 1, with comments below. >> > >> > 1. Use unmapped cached region utilization in the MIPS32 ioremap_pro= t() >> > method. >> > This solution a bit clumsy than it looks on the first glance. >> > ioremap_prot() can be used for various types of the cachability >> > mapping. Currently it's a default-cacheable CA preserved in the >> > _page_cachable_default variable and Write-combined CA saved in >> > boot_cpu_data.writecombine. Based on that we would have needed to u= se >> > the unmapped cached region utilized for the IO-remaps called with t= he >> > "_page_cachable_default" mapping flags passed only. The rest of the= IO >> > range mappings, including the write-combined ones, would have been >> > handled by VM means. This would have made the ioremap_prot() a bit >> > less maintainable, but still won't be that hard to implement (unles= s I >> > miss something): >> > --- a/arch/mips/mm/ioremap.c >> > +++ b/arch/mips/mm/ioremap.c >> > /* >> > - * Map uncached objects in the low 512mb of address space u= sing KSEG1, >> > - * otherwise map using page tables. >> > + * Map uncached/default-cached objects in the low 512mb of = address >> > + * space using KSEG1/KSEG0, otherwise map using page tables. >> > */ >> > - if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) && >> > - flags =3D=3D _CACHE_UNCACHED) >> > - return (void __iomem *) CKSEG1ADDR(phys_addr); >> > + if (IS_LOW512(phys_addr) && IS_LOW512(last_addr)) { >> > + if (flags =3D=3D _CACHE_UNCACHED) >> > + return (void __iomem *) CKSEG1ADDR(phys_add= r); >> > + else if (flags =3D=3D _page_cachable_default) >> > + return (void __iomem *) CKSEG0ADDR(phys_add= r); >> > + } >> > >> > Currently I can't figure out what obvious problems it may cause. But >> > It seems suspicious that the cacheable IO-mapping hasn't been >> > implemented by the unmapped cacheable region in the first place. In >> > anyway this solution looks more dangerous than solution 2. because = it >> > affects all the MIPS32 platforms at once. >>=20 >> I just made a quick grep in tree, and it seems like we don't have much >> user of ioremap_cache (as well as ioremap_uc/wc) here so I think it is >> a safe assumption. > > I wouldn't say there aren't much users. ioremap_wc() and it's > devm-version is widely utilized in the GPU and network and some other > subsystems. ioremap_cache() isn't widespread indeed. In anyway even a > single user must be supported in safely calling the method if it's > provided by the arch-code, otherwise the method could be considered as > just a bogus stub to have the kernel successfully built. I bet you'll > agree with that. But that's not the point in this case. ioremap_wc() is useful for mapping PCI attached memory such as frame buffers, but ioremap_cache() is generally underspecified because the resulting pointer is neither safe to dereference nor to pass into readl()/writel()/memcpy_fromio() on all architectures. There was an effort to convert the remaining ioremap_cache() calls into memremap() a few years ago, not sure if that's still being worked on but it would be the right thing to do. Arnd