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Wed, 29 Nov 2023 00:29:09 -0800 (PST) Hi Sascha, On 11/27/23 19:19, Sascha Hauer wrote: > Hi Andy, > > Looks good overall, two small things inside. > > On Wed, Nov 22, 2023 at 08:55:44PM +0800, Andy Yan wrote: >> >> +#define vop2_output_if_is_hdmi(x) (x == ROCKCHIP_VOP2_EP_HDMI0 || x == ROCKCHIP_VOP2_EP_HDMI1) >> +#define vop2_output_if_is_dp(x) (x == ROCKCHIP_VOP2_EP_DP0 || x == ROCKCHIP_VOP2_EP_DP1) >> +#define vop2_output_if_is_edp(x) (x == ROCKCHIP_VOP2_EP_EDP0 || x == ROCKCHIP_VOP2_EP_EDP1) >> +#define vop2_output_if_is_mipi(x) (x == ROCKCHIP_VOP2_EP_MIPI0 || x == ROCKCHIP_VOP2_EP_MIPI1) >> +#define vop2_output_if_is_lvds(x) (x == ROCKCHIP_VOP2_EP_LVDS0 || x == ROCKCHIP_VOP2_EP_LVDS1) >> +#define vop2_output_if_is_dpi(x) (x == ROCKCHIP_VOP2_EP_RGB0) > Not that it matters in practice here, but you should add braces around > the x argument in the macros usage, i.e. ((x) == ROCKCHIP_VOP2_EP_RGB0) Okay , will do. >> +static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags) >> +{ >> + struct vop2 *vop2 = vp->vop2; >> + int dclk_core_div, dclk_out_div, if_pixclk_div, if_dclk_div; >> + unsigned long clock; >> + u32 die, dip, div, vp_clk_div, val; >> + >> + clock = rk3588_calc_cru_cfg(vp, id, &dclk_core_div, &dclk_out_div, >> + &if_pixclk_div, &if_dclk_div); >> + if (!clock) >> + return 0; >> + >> + vp_clk_div = FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_CORE_DIV, dclk_core_div); >> + vp_clk_div |= FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_OUT_DIV, dclk_out_div); >> + >> + die = vop2_readl(vop2, RK3568_DSP_IF_EN); >> + dip = vop2_readl(vop2, RK3568_DSP_IF_POL); >> + div = vop2_readl(vop2, RK3568_DSP_IF_CTRL); >> + >> + switch (id) { >> + case ROCKCHIP_VOP2_EP_HDMI0: >> + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div); > you should clear the bits of a mask before setting them again. The same > goes for several other bits modified in this switch/case. Thanks for catching this, will fixed in next version. > >> + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div); >> + die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX; >> + die |= RK3588_SYS_DSP_INFACE_EN_HDMI0 | >> + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id); >> + val = rk3588_get_hdmi_pol(polflags); >> + regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 1, 1)); >> + regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 6, 5)); >> + break; > Sascha >