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Wed, 29 Nov 2023 10:34:22 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ATAYL6w003692 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Nov 2023 10:34:22 GMT Received: from [10.253.72.234] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 29 Nov 2023 02:34:19 -0800 Message-ID: <277a4cdf-fef6-4d40-baac-01d5da40ce62@quicinc.com> Date: Wed, 29 Nov 2023 18:34:16 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 3/6] net: phy: at803x: add QCA8084 ethernet phy support To: "Russell King (Oracle)" CC: Andrew Lunn , , , , , , , , , , , , , References: <20231126060732.31764-1-quic_luoj@quicinc.com> <20231126060732.31764-4-quic_luoj@quicinc.com> <0b22dd51-417c-436d-87ce-7ebc41185860@lunn.ch> <8e4046dd-813c-4766-83fb-c54a700caf31@lunn.ch> <9c4c1fe7-5d71-4bb2-8b92-f4e9a136e93d@quicinc.com> Content-Language: en-US From: Jie Luo In-Reply-To: Content-Type: text/plain; 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Wed, 29 Nov 2023 02:34:49 -0800 (PST) On 11/28/2023 6:35 PM, Russell King (Oracle) wrote: > On Tue, Nov 28, 2023 at 05:50:41PM +0800, Jie Luo wrote: >> >> >> On 11/28/2023 5:00 PM, Russell King (Oracle) wrote: >>> On Tue, Nov 28, 2023 at 03:16:45PM +0800, Jie Luo wrote: >>>>>> The interface mode is passed in the .config_init, which is configured >>>>>> by the PCS driver, the hardware register is located in the PCS, this >>>>>> driver will be pushed later. >>>>> >>>>> Is this the same as how the syqca807x works? Can the PCS driver be >>>>> shared by these two drivers? >>>> >>>> I am not sure syqca807x, would you point me the code path of this driver? >>>> >>>>> >>>>> What i don't like at the moment is that we have two driver >>>>> developments going on at once for hardware which seems very similar, >>>>> but no apparent cooperation? >>>>> >>>>> Andrew >>>> >>>> The PCS of qca8084 is the PHY PCS, which should be new PCS driver, >>>> in the previous chips, we don't have this kind of PHY PCS. >>> >>> No. PCS drivers are for MAC-side PCS drivers, not PHY-side PCS drivers. >>> >>> +------------- >>> | PHY >>> MAC---PCS --- link --- PCS --- ... >>> ^ | ^ >>> | +--|---------- >>> For this PCS | >>> Not for this PCS >>> >> >> The PCS drivers in drivers/net/pcs/ should be in PHY side, such as >> pcs-lynx.c and pcs-xpcs.c, they are configuring the MDIO device >> registers. > > Wrong. No they are not. Just because they are accessed via MDIO does > not mean they are in the PHY. MDIO can be used for more than just the > PHY, and is on a lot of platforms. > > LX2160A for example has many MDIO buses, and the PCSes (of which there > are multiple inside the chip, and use pcs-lynx) are accessed through > the MDIO bus specific to each port. They are not MMIO mapped. > > The same is true on stmmac platforms, where xpcs is used - xpcs is the > _MAC_ side PCS. > > Sorry but you are wrong. > OK, but it creates the PCS driver based on the MDIO device in pcs-lynx.c looks like this PCS is located in PHY device from hardware perspective.