Received: by 2002:a05:7412:419a:b0:f3:1519:9f41 with SMTP id i26csp4476824rdh; Wed, 29 Nov 2023 02:35:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IGa+io+ksnH5MLrDvUEFwXwMb0sT2MrzCPZtAQV0D2pzleztpia5UjJOpuo83cgEVuRKWhg X-Received: by 2002:a17:902:f805:b0:1cf:ad71:6f64 with SMTP id ix5-20020a170902f80500b001cfad716f64mr12230415plb.59.1701254122463; Wed, 29 Nov 2023 02:35:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701254122; cv=none; d=google.com; s=arc-20160816; b=z6RnADtlmPCSEsffAoMjjQrdRZx9n+3eSkIWZuZaw1wYDoByZ1QKexs1RR8lsz21A5 umeEr5f6DjgveZmlU0LZ+aPQmjVXL97v5N0cjtyYb0fKXkGP5fg27hlJsvrxDfV5qy61 rt6unruC/9gJSw+XtgBRXJkuk9toow+E9fxQU8K4NxRJ3DKxMTTwDTQqOF9BLOQi0QhE ryuumuHW8XiPuy1VfxL5/K3kjK0a/L/K3mlmz0dpCXw4eYZNbYn7U//T/gL3f0u0/LbO sMJ5jT8SRRFYvFxVgXFogugdrTK7NCYPmkujMB1XcQt5y4QKywyJXDG6x80OkMIeFOpF q2hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=9aKw33tkZUmmjCc4Ct2HtcxVzDFPWx1ytcAMCjGjDKs=; fh=jLcIigoZUJbU7n3xFGZfVKYHbDRfSbM5FBZqXG+l2kE=; b=V2BJpXy9D6QtMl3gkguyqPnd2gIlQH0TPD60oI+E5CaHHNffi3ujsrU0KREKieayLy hbagQN7yrVMUkQo1arMKbllOdDx7xhDEhj2ISbIMQx6l7ZcgYe3nv8VHndnDkuvyFVoW e215oD5B5p+dJ1lfsQFtslopnISP8iQNETAZyLKqi2UIdbupQjp0VUF557+E9QgBo7tm y6LdIdGFOmtDurHeRODgrrFPDR0hBJBjiRuwfPTvF4zJWFk8IQ2vJblSNIVBP2EN7v5K Elasouo6ZqBMX5pdr2G7mBiBrWhVOOlJw0sHdO+nFaqcjMslris7Au3e1eqyiViGT/kN zNwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=K22wviub; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id 6-20020a170902ee4600b001bbca0a8393si13739166plo.56.2023.11.29.02.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 02:35:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=K22wviub; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 5B76980C591D; Wed, 29 Nov 2023 02:35:21 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229954AbjK2KfG (ORCPT + 99 others); Wed, 29 Nov 2023 05:35:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230081AbjK2KfC (ORCPT ); Wed, 29 Nov 2023 05:35:02 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5918D1BC0; Wed, 29 Nov 2023 02:34:46 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AT3H8ue001545; Wed, 29 Nov 2023 10:34:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=9aKw33tkZUmmjCc4Ct2HtcxVzDFPWx1ytcAMCjGjDKs=; b=K22wviubYoJ5QcBJ4AX2poFetwERhbnAOJY7+oE6sLs2ZGcqvwNy7u/9ZIENC9G0n3jj bmcs7ecLEDst8mQUsB5brSoBwEPFLBfUBMEwvb9HPGBh+gRODrWEP4WDeB/0RFHE1rrd y+ptHCVcswzgnfFVFQPTTwkySpeJkp3HkyKVw7YNqHKi2KC38U5yeuMkbCTp0rQh0Uuy 4BEApUrK+r6rJcd0krmF30XxYFhKYp6/Mo9WwCkH+0OIfP0MVunIGxLzKkBCMbsCHrdc kD29tUNZOXqPdHJ9iaKT+rSn1IejdajPfaPAn9BqqO1mlKvU0FsoyQ/H6EtuOFE56a5W OA== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3unnpesytk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Nov 2023 10:34:43 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ATAYgwU003908 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Nov 2023 10:34:42 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 29 Nov 2023 02:34:37 -0800 From: Tengfei Fan To: , , , , , CC: , , , , Tengfei Fan Subject: [PATCH v7 3/6] arm64: dts: qcom: add uart console support for SM4450 Date: Wed, 29 Nov 2023 18:33:22 +0800 Message-ID: <20231129103325.24854-4-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231129103325.24854-1-quic_tengfan@quicinc.com> References: <20231129103325.24854-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hGyOiqY-5TYuNewaSdDU6Owz1-yH39QG X-Proofpoint-ORIG-GUID: hGyOiqY-5TYuNewaSdDU6Owz1-yH39QG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-29_07,2023-11-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 mlxscore=0 phishscore=0 mlxlogscore=815 priorityscore=1501 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311290078 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 29 Nov 2023 02:35:21 -0800 (PST) Add base description of UART and TLMM nodes which helps SM4450 boot to shell with console on boards with this SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Tengfei Fan --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 49 ++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index 5a8a54b0f6c1..3e7ae3bebbe0 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -364,6 +364,29 @@ <0>; }; + qupv3_id_0: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + ranges; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + uart7: serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a88000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = ; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -380,6 +403,32 @@ interrupt-controller; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sm4450-tlmm"; + reg = <0x0 0x0f100000 0x0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 137>; + wakeup-parent = <&pdc>; + + qup_uart7_rx: qup-uart7-rx-state { + pins = "gpio23"; + function = "qup1_se2_l2"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins = "gpio22"; + function = "qup1_se2_l2"; + drive-strength = <2>; + bias-disable; + }; + }; + intc: interrupt-controller@17200000 { compatible = "arm,gic-v3"; reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ -- 2.17.1