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Wed, 29 Nov 2023 10:50:26 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ATAoPRZ019480 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Nov 2023 10:50:25 GMT Received: from [10.216.28.66] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 29 Nov 2023 02:50:20 -0800 Message-ID: <3abe4ebe-80fc-4214-b01e-50c25575f2b9@quicinc.com> Date: Wed, 29 Nov 2023 16:20:16 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] dt-bindings: usb: dwc3: Clean up hs_phy_irq in bindings To: Johan Hovold , Krzysztof Kozlowski CC: Andy Gross , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , , , , , , , References: <20231122191335.3058-1-quic_kriskura@quicinc.com> <1192d91f-11bf-44af-953a-14e08e2b6ca8@quicinc.com> <004ddc69-1566-4de4-b260-0fca96a9395f@quicinc.com> <18965bb9-7afa-4892-8b71-981ba29d2cd4@quicinc.com> <6d7527bf-8c1a-49b5-a0cf-99a92098c971@quicinc.com> Content-Language: en-US From: Krishna Kurapati PSSNV In-Reply-To: Content-Type: text/plain; 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Wed, 29 Nov 2023 02:50:35 -0800 (PST) On 11/29/2023 3:46 PM, Johan Hovold wrote: > On Wed, Nov 29, 2023 at 10:28:25AM +0100, Krzysztof Kozlowski wrote: >> On 28/11/2023 12:32, Krishna Kurapati PSSNV wrote: >>> >>>> >>>> So back to my initial proposal, with a slight modification moving >>>> pwr_event first (e.g. as it is not a wakeup interrupt): >>>> >>>> qusb2-: >>>> >>>> - const: pwr_event >>>> - const: qusb2_phy >>>> - const: ss_phy_irq (optional) >>>> >>>> qusb2: >>>> >>>> - const: pwr_event >>>> - const: hs_phy_irq >>>> - const: qusb2_phy >>>> - const: ss_phy_irq (optional) >>>> >>>> femto-: >>>> - const: pwr_event >>>> - const: dp_hs_phy_irq >>>> - const: dm_hs_phy_irq >>>> - const: ss_phy_irq (optional) >>>> >>>> femto: >>>> - const: pwr_event >>>> - const: hs_phy_irq >>>> - const: dp_hs_phy_irq >>>> - const: dm_hs_phy_irq >>>> - const: ss_phy_irq (optional) >> >> I did not follow entire thread and I do not know whether you change the >> order in existing bindings, but just in case: the entries in existing >> bindings cannot change the order. That's a strict ABI requirement >> recently also discussed with Bjorn, because we want to have stable DTB >> for laptop platforms. If my comment is not relevant, then please ignore. > > Your comment is relevant, but I'm not sure I agree. > > The Qualcomm bindings are a complete mess of DT snippets copied from > vendor trees and which have not been sanitised properly before being > merged upstream (partly due to there not being any public documentation > available). > > This amounts to an unmaintainable mess which is reflected in the > binding schemas which similarly needs to encode every random order which > the SoC happened to use when being upstreamed. That makes the binding > documentation unreadable too, and the next time a new SoC is upstreamed > there is no clear hints of what the binding should look like, and we end > up with yet another permutation. > > As part of this exercise, we've also determined that some of the > devicetrees that are already upstream are incorrect as well as > incomplete. > > I really see no alternative to ripping of the plaster and cleaning this > up once and for all even if it "breaks" some imaginary OS which (unlike > Linux) relies on the current random order of these interrupts. > > [ If there were any real OSes actually relying on the order, then that > would be a different thing of course. ] > Hi Krzysztof, Johan, We are modifying all the DT's in accordance to bindings as well. Still it would be breaking ABI ? Regards, Krishna,