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Message-ID: <6a26b0c9-cbea-4ca2-bc16-79ed53e3a6fe@amd.com>
Date:   Wed, 29 Nov 2023 16:47:03 +0100
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH] drm/radeon/r600_cs: Fix possible int overflows in
 r600_cs_check_reg()
Content-Language: en-US
To:     Nikita Zhandarovich <n.zhandarovich@fintech.ru>,
        Alex Deucher <alexander.deucher@amd.com>
Cc:     "Pan, Xinhui" <Xinhui.Pan@amd.com>,
        David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>, amd-gfx@lists.freedesktop.org,
        dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
References: <20231129152230.7931-1-n.zhandarovich@fintech.ru>
From:   =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>
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 =?utf-8?B?OVFETVRHek5vLzBNRFEweWNMU0pNOTlHaSt6enAwekhxdURtVnFHbEZ2d2hF?=
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Am 29.11.23 um 16:22 schrieb Nikita Zhandarovich:
> While improbable, there may be a chance of hitting integer
> overflow when the result of radeon_get_ib_value() gets shifted
> left.
>
> Avoid it by casting one of the operands to larger data type (u64).
>
> Found by Linux Verification Center (linuxtesting.org) with static
> analysis tool SVACE.

Well IIRC cb_color_bo_offset is just 32bits anyway, so this doesn't 
change anything.

Regards,
Christian.

>
> Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes")
> Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru>
> ---
>   drivers/gpu/drm/radeon/r600_cs.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
> index 638f861af80f..6cf54a747749 100644
> --- a/drivers/gpu/drm/radeon/r600_cs.c
> +++ b/drivers/gpu/drm/radeon/r600_cs.c
> @@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
>   			return -EINVAL;
>   		}
>   		tmp = (reg - CB_COLOR0_BASE) / 4;
> -		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
> +		track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
>   		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
>   		track->cb_color_base_last[tmp] = ib[idx];
>   		track->cb_color_bo[tmp] = reloc->robj;
> @@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
>   					"0x%04X\n", reg);
>   			return -EINVAL;
>   		}
> -		track->htile_offset = radeon_get_ib_value(p, idx) << 8;
> +		track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
>   		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
>   		track->htile_bo = reloc->robj;
>   		track->db_dirty = true;